tuxmain/w5100-rs
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Added self to authors list, fixed Clippy lint errors

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This commit is contained in:
Jonah Dahlquist 2020-11-22 13:15:33 -08:00
commit 1cac758d5a
9 changed files with 59 additions and 55 deletions
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2
Cargo.toml
View file

@ -1,7 +1,7 @@
[package] [package]
name = "w5500" name = "w5500"
version = "0.3.0" version = "0.3.0"
authors = ["Michael Watzko <michael@watzko.de>"] authors = ["Michael Watzko <michael@watzko.de>", "Jonah Dahlquist <hi@jonah.name>"]
repository = "https://github.com/kellerkindt/w5500.git" repository = "https://github.com/kellerkindt/w5500.git"
description = "W5500 IoT Controller implementation. Currently UDP sending and receiving is working. WIP" description = "W5500 IoT Controller implementation. Currently UDP sending and receiving is working. WIP"
keywords = ["embedded", "w5500", "iot", "arm", "embedded-hal-driver"] keywords = ["embedded", "w5500", "iot", "arm", "embedded-hal-driver"]

22
src/bus/four_wire.rs
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@ -1,3 +1,5 @@
#![allow(clippy::unusual_byte_groupings)]
use core::fmt; use core::fmt;
use embedded_hal::digital::v2::OutputPin; use embedded_hal::digital::v2::OutputPin;
use embedded_hal::spi::FullDuplex; use embedded_hal::spi::FullDuplex;
@ -38,16 +40,12 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
let address_phase = address.to_be_bytes(); let address_phase = address.to_be_bytes();
let control_phase = block << 3; let control_phase = block << 3;
let data_phase = data; let data_phase = data;
self.cs self.cs.set_low().map_err(FourWireError::ChipSelectError)?;
.set_low()
.map_err(|e| FourWireError::ChipSelectError(e))?;
Self::write_bytes(&mut self.spi, &address_phase) Self::write_bytes(&mut self.spi, &address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, control_phase)) .and_then(|_| Self::transfer_byte(&mut self.spi, control_phase))
.and_then(|_| Self::read_bytes(&mut self.spi, data_phase)) .and_then(|_| Self::read_bytes(&mut self.spi, data_phase))
.map_err(|e| FourWireError::SpiError(e))?; .map_err(FourWireError::SpiError)?;
self.cs self.cs.set_high().map_err(FourWireError::ChipSelectError)?;
.set_high()
.map_err(|e| FourWireError::ChipSelectError(e))?;
Ok(()) Ok(())
} }
@ -55,16 +53,12 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
let address_phase = address.to_be_bytes(); let address_phase = address.to_be_bytes();
let control_phase = block << 3 | WRITE_MODE_MASK; let control_phase = block << 3 | WRITE_MODE_MASK;
let data_phase = data; let data_phase = data;
self.cs self.cs.set_low().map_err(FourWireError::ChipSelectError)?;
.set_low()
.map_err(|e| FourWireError::ChipSelectError(e))?;
Self::write_bytes(&mut self.spi, &address_phase) Self::write_bytes(&mut self.spi, &address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, control_phase)) .and_then(|_| Self::transfer_byte(&mut self.spi, control_phase))
.and_then(|_| Self::write_bytes(&mut self.spi, data_phase)) .and_then(|_| Self::write_bytes(&mut self.spi, data_phase))
.map_err(|e| FourWireError::SpiError(e))?; .map_err(FourWireError::SpiError)?;
self.cs self.cs.set_high().map_err(FourWireError::ChipSelectError)?;
.set_high()
.map_err(|e| FourWireError::ChipSelectError(e))?;
Ok(()) Ok(())
} }

16
src/bus/three_wire.rs
View file

@ -1,3 +1,5 @@
#![allow(clippy::unusual_byte_groupings)]
use core::fmt; use core::fmt;
use embedded_hal::spi::FullDuplex; use embedded_hal::spi::FullDuplex;
@ -17,6 +19,12 @@ impl ThreeWire {
} }
} }
impl Default for ThreeWire {
fn default() -> Self {
Self::new()
}
}
impl Bus for ThreeWire {} impl Bus for ThreeWire {}
impl ThreeWire { impl ThreeWire {
@ -53,7 +61,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
let mut data_phase = &mut data[..]; let mut data_phase = &mut data[..];
let mut last_length_written: u16; let mut last_length_written: u16;
while data_phase.len() > 0 { while !data_phase.is_empty() {
if data_phase.len() >= 4 { if data_phase.len() >= 4 {
control_phase |= FIXED_DATA_LENGTH_MODE_4; control_phase |= FIXED_DATA_LENGTH_MODE_4;
last_length_written = 4; last_length_written = 4;
@ -74,7 +82,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
&mut data_phase[..last_length_written as usize], &mut data_phase[..last_length_written as usize],
) )
}) })
.map_err(|e| ThreeWireError::SpiError(e))?; .map_err(ThreeWireError::SpiError)?;
address += last_length_written; address += last_length_written;
data_phase = &mut data_phase[last_length_written as usize..]; data_phase = &mut data_phase[last_length_written as usize..];
@ -86,7 +94,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
let mut data_phase = &data[..]; let mut data_phase = &data[..];
let mut last_length_written: u16; let mut last_length_written: u16;
while data_phase.len() > 0 { while !data_phase.is_empty() {
if data_phase.len() >= 4 { if data_phase.len() >= 4 {
control_phase |= FIXED_DATA_LENGTH_MODE_4; control_phase |= FIXED_DATA_LENGTH_MODE_4;
last_length_written = 4; last_length_written = 4;
@ -104,7 +112,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
.and_then(|_| { .and_then(|_| {
Self::write_bytes(&mut self.spi, &data_phase[..last_length_written as usize]) Self::write_bytes(&mut self.spi, &data_phase[..last_length_written as usize])
}) })
.map_err(|e| ThreeWireError::SpiError(e))?; .map_err(ThreeWireError::SpiError)?;
address += last_length_written; address += last_length_written;
data_phase = &data_phase[last_length_written as usize..]; data_phase = &data_phase[last_length_written as usize..];

6
src/device.rs
View file

@ -46,9 +46,9 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network> Device<SpiBus, NetworkImpl> {
fn clear_mode(&mut self) -> Result<(), SpiBus::Error> { fn clear_mode(&mut self) -> Result<(), SpiBus::Error> {
// reset bit // reset bit
let mut mode = [0b10000000]; let mode = [0b10000000];
self.bus self.bus
.write_frame(register::COMMON, register::common::MODE, &mut mode)?; .write_frame(register::COMMON, register::common::MODE, &mode)?;
Ok(()) Ok(())
} }
@ -73,7 +73,7 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network> Device<SpiBus, NetworkImpl> {
self.into() self.into()
} }
pub fn release_socket(&mut self, socket: Socket) -> () { pub fn release_socket(&mut self, socket: Socket) {
self.sockets.set_bit(socket.index.into(), true); self.sockets.set_bit(socket.index.into(), true);
} }

8
src/network/mod.rs
View file

@ -50,13 +50,13 @@ pub trait Network {
current.subnet = settings.subnet; current.subnet = settings.subnet;
} }
if settings.mac != current.mac { if settings.mac != current.mac {
let mut address = settings.mac.address; let address = settings.mac.octets;
bus.write_frame(register::COMMON, register::common::MAC, &mut address)?; bus.write_frame(register::COMMON, register::common::MAC, &address)?;
current.mac = settings.mac; current.mac = settings.mac;
} }
if settings.ip != current.ip { if settings.ip != current.ip {
let mut address = settings.ip.octets(); let address = settings.ip.octets();
bus.write_frame(register::COMMON, register::common::IP, &mut address)?; bus.write_frame(register::COMMON, register::common::IP, &address)?;
current.ip = settings.ip; current.ip = settings.ip;
} }
Ok(()) Ok(())

2
src/register.rs
View file

@ -1,3 +1,5 @@
#![allow(clippy::unusual_byte_groupings)]
pub const COMMON: u8 = 0; pub const COMMON: u8 = 0;
pub mod common { pub mod common {
use bit_field::BitArray; use bit_field::BitArray;

40
src/socket.rs
View file

@ -45,8 +45,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
mode: socketn::Protocol, mode: socketn::Protocol,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut mode = [mode as u8]; let mode = [mode as u8];
bus.write_frame(self.register(), socketn::MODE, &mut mode)?; bus.write_frame(self.register(), socketn::MODE, &mode)?;
Ok(()) Ok(())
} }
@ -55,8 +55,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
code: socketn::Interrupt, code: socketn::Interrupt,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [code as u8]; let data = [code as u8];
bus.write_frame(self.register(), socketn::INTERRUPT, &mut data)?; bus.write_frame(self.register(), socketn::INTERRUPT, &data)?;
Ok(()) Ok(())
} }
@ -75,8 +75,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
port: u16, port: u16,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = port.to_be_bytes(); let data = port.to_be_bytes();
bus.write_frame(self.register(), socketn::SOURCE_PORT, &mut data)?; bus.write_frame(self.register(), socketn::SOURCE_PORT, &data)?;
Ok(()) Ok(())
} }
@ -85,8 +85,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
ip: Ipv4Addr, ip: Ipv4Addr,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = ip.octets(); let data = ip.octets();
bus.write_frame(self.register(), socketn::DESTINATION_IP, &mut data)?; bus.write_frame(self.register(), socketn::DESTINATION_IP, &data)?;
Ok(()) Ok(())
} }
@ -95,8 +95,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
port: u16, port: u16,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = port.to_be_bytes(); let data = port.to_be_bytes();
bus.write_frame(self.register(), socketn::DESTINATION_PORT, &mut data)?; bus.write_frame(self.register(), socketn::DESTINATION_PORT, &data)?;
Ok(()) Ok(())
} }
@ -114,8 +114,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
pointer: u16, pointer: u16,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = pointer.to_be_bytes(); let data = pointer.to_be_bytes();
bus.write_frame(self.register(), socketn::TX_DATA_READ_POINTER, &mut data)?; bus.write_frame(self.register(), socketn::TX_DATA_READ_POINTER, &data)?;
Ok(()) Ok(())
} }
@ -133,8 +133,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
pointer: u16, pointer: u16,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = pointer.to_be_bytes(); let data = pointer.to_be_bytes();
bus.write_frame(self.register(), socketn::TX_DATA_WRITE_POINTER, &mut data)?; bus.write_frame(self.register(), socketn::TX_DATA_WRITE_POINTER, &data)?;
Ok(()) Ok(())
} }
@ -152,8 +152,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
pointer: u16, pointer: u16,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = pointer.to_be_bytes(); let data = pointer.to_be_bytes();
bus.write_frame(self.register(), socketn::RX_DATA_READ_POINTER, &mut data)?; bus.write_frame(self.register(), socketn::RX_DATA_READ_POINTER, &data)?;
Ok(()) Ok(())
} }
@ -162,8 +162,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
mask: u8, mask: u8,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [mask]; let data = [mask];
bus.write_frame(self.register(), socketn::INTERRUPT_MASK, &mut data)?; bus.write_frame(self.register(), socketn::INTERRUPT_MASK, &data)?;
Ok(()) Ok(())
} }
@ -172,8 +172,8 @@ impl Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
command: socketn::Command, command: socketn::Command,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [command as u8]; let data = [command as u8];
bus.write_frame(self.register(), socketn::COMMAND, &mut data)?; bus.write_frame(self.register(), socketn::COMMAND, &data)?;
Ok(()) Ok(())
} }

2
src/udp.rs
View file

@ -121,7 +121,7 @@ impl UdpSocket {
self.socket self.socket
.set_rx_read_pointer(bus, tx_write_pointer) .set_rx_read_pointer(bus, tx_write_pointer)
.and_then(|_| self.socket.command(bus, socketn::Command::Receive))?; .and_then(|_| self.socket.command(bus, socketn::Command::Receive))?;
Ok((packet_size.into(), remote)) Ok((packet_size, remote))
} }
fn close<SpiBus: ActiveBus>( fn close<SpiBus: ActiveBus>(

16
src/uninitialized_device.rs
View file

@ -20,7 +20,7 @@ pub enum InitializeError<SpiError> {
impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> { impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
pub fn new(bus: SpiBus) -> UninitializedDevice<SpiBus> { pub fn new(bus: SpiBus) -> UninitializedDevice<SpiBus> {
UninitializedDevice { bus: bus } UninitializedDevice { bus }
} }
pub fn initialize( pub fn initialize(
@ -65,16 +65,16 @@ impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
self.assert_chip_version(0x4)?; self.assert_chip_version(0x4)?;
// RESET // RESET
let mut mode = [0b10000000]; let mode = [0b10000000];
self.bus self.bus
.write_frame(register::COMMON, register::common::MODE, &mut mode) .write_frame(register::COMMON, register::common::MODE, &mode)
.map_err(|e| InitializeError::SpiError(e))?; .map_err(InitializeError::SpiError)?;
self.set_mode(mode_options) self.set_mode(mode_options)
.map_err(|e| InitializeError::SpiError(e))?; .map_err(InitializeError::SpiError)?;
network network
.refresh(&mut self.bus) .refresh(&mut self.bus)
.map_err(|e| InitializeError::SpiError(e))?; .map_err(InitializeError::SpiError)?;
Ok(Device::new(self.bus, network)) Ok(Device::new(self.bus, network))
} }
@ -85,7 +85,7 @@ impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
let mut version = [0]; let mut version = [0];
self.bus self.bus
.read_frame(register::COMMON, register::common::VERSION, &mut version) .read_frame(register::COMMON, register::common::VERSION, &mut version)
.map_err(|e| InitializeError::SpiError(e))?; .map_err(InitializeError::SpiError)?;
if version[0] != expected_version { if version[0] != expected_version {
Err(InitializeError::ChipNotConnected) Err(InitializeError::ChipNotConnected)
} else { } else {
@ -100,7 +100,7 @@ impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
mode[0] |= mode_options.connection_type as u8; mode[0] |= mode_options.connection_type as u8;
mode[0] |= mode_options.arp_responses as u8; mode[0] |= mode_options.arp_responses as u8;
self.bus self.bus
.write_frame(register::COMMON, register::common::MODE, &mut mode)?; .write_frame(register::COMMON, register::common::MODE, &mode)?;
Ok(()) Ok(())
} }
} }