diff --git a/Cargo.toml b/Cargo.toml
index 6fdcb9c..4d99c18 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,7 +1,7 @@
 [package]
 name = "w5500"
 version = "0.3.0"
-authors = ["Michael Watzko <michael@watzko.de>"]
+authors = ["Michael Watzko <michael@watzko.de>", "Jonah Dahlquist <hi@jonah.name>"]
 repository = "https://github.com/kellerkindt/w5500.git"
 description = "W5500 IoT Controller implementation. Currently UDP sending and receiving is working. WIP"
 keywords = ["embedded", "w5500", "iot", "arm", "embedded-hal-driver"]
diff --git a/src/bus/four_wire.rs b/src/bus/four_wire.rs
index ffdf7d1..7c31a51 100644
--- a/src/bus/four_wire.rs
+++ b/src/bus/four_wire.rs
@@ -1,3 +1,5 @@
+#![allow(clippy::unusual_byte_groupings)]
+
 use core::fmt;
 use embedded_hal::digital::v2::OutputPin;
 use embedded_hal::spi::FullDuplex;
@@ -38,16 +40,12 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
         let address_phase = address.to_be_bytes();
         let control_phase = block << 3;
         let data_phase = data;
-        self.cs
-            .set_low()
-            .map_err(|e| FourWireError::ChipSelectError(e))?;
+        self.cs.set_low().map_err(FourWireError::ChipSelectError)?;
         Self::write_bytes(&mut self.spi, &address_phase)
             .and_then(|_| Self::transfer_byte(&mut self.spi, control_phase))
             .and_then(|_| Self::read_bytes(&mut self.spi, data_phase))
-            .map_err(|e| FourWireError::SpiError(e))?;
-        self.cs
-            .set_high()
-            .map_err(|e| FourWireError::ChipSelectError(e))?;
+            .map_err(FourWireError::SpiError)?;
+        self.cs.set_high().map_err(FourWireError::ChipSelectError)?;
 
         Ok(())
     }
@@ -55,16 +53,12 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
         let address_phase = address.to_be_bytes();
         let control_phase = block << 3 | WRITE_MODE_MASK;
         let data_phase = data;
-        self.cs
-            .set_low()
-            .map_err(|e| FourWireError::ChipSelectError(e))?;
+        self.cs.set_low().map_err(FourWireError::ChipSelectError)?;
         Self::write_bytes(&mut self.spi, &address_phase)
             .and_then(|_| Self::transfer_byte(&mut self.spi, control_phase))
             .and_then(|_| Self::write_bytes(&mut self.spi, data_phase))
-            .map_err(|e| FourWireError::SpiError(e))?;
-        self.cs
-            .set_high()
-            .map_err(|e| FourWireError::ChipSelectError(e))?;
+            .map_err(FourWireError::SpiError)?;
+        self.cs.set_high().map_err(FourWireError::ChipSelectError)?;
 
         Ok(())
     }
diff --git a/src/bus/three_wire.rs b/src/bus/three_wire.rs
index e6cf71a..efde49c 100644
--- a/src/bus/three_wire.rs
+++ b/src/bus/three_wire.rs
@@ -1,3 +1,5 @@
+#![allow(clippy::unusual_byte_groupings)]
+
 use core::fmt;
 use embedded_hal::spi::FullDuplex;
 
@@ -17,6 +19,12 @@ impl ThreeWire {
     }
 }
 
+impl Default for ThreeWire {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl Bus for ThreeWire {}
 
 impl ThreeWire {
@@ -53,7 +61,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
 
         let mut data_phase = &mut data[..];
         let mut last_length_written: u16;
-        while data_phase.len() > 0 {
+        while !data_phase.is_empty() {
             if data_phase.len() >= 4 {
                 control_phase |= FIXED_DATA_LENGTH_MODE_4;
                 last_length_written = 4;
@@ -74,7 +82,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
                         &mut data_phase[..last_length_written as usize],
                     )
                 })
-                .map_err(|e| ThreeWireError::SpiError(e))?;
+                .map_err(ThreeWireError::SpiError)?;
 
             address += last_length_written;
             data_phase = &mut data_phase[last_length_written as usize..];
@@ -86,7 +94,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
 
         let mut data_phase = &data[..];
         let mut last_length_written: u16;
-        while data_phase.len() > 0 {
+        while !data_phase.is_empty() {
             if data_phase.len() >= 4 {
                 control_phase |= FIXED_DATA_LENGTH_MODE_4;
                 last_length_written = 4;
@@ -104,7 +112,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
                 .and_then(|_| {
                     Self::write_bytes(&mut self.spi, &data_phase[..last_length_written as usize])
                 })
-                .map_err(|e| ThreeWireError::SpiError(e))?;
+                .map_err(ThreeWireError::SpiError)?;
 
             address += last_length_written;
             data_phase = &data_phase[last_length_written as usize..];
diff --git a/src/device.rs b/src/device.rs
index ee92e05..833ed4c 100644
--- a/src/device.rs
+++ b/src/device.rs
@@ -46,9 +46,9 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network> Device<SpiBus, NetworkImpl> {
 
     fn clear_mode(&mut self) -> Result<(), SpiBus::Error> {
         // reset bit
-        let mut mode = [0b10000000];
+        let mode = [0b10000000];
         self.bus
-            .write_frame(register::COMMON, register::common::MODE, &mut mode)?;
+            .write_frame(register::COMMON, register::common::MODE, &mode)?;
         Ok(())
     }
 
@@ -73,7 +73,7 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network> Device<SpiBus, NetworkImpl> {
         self.into()
     }
 
-    pub fn release_socket(&mut self, socket: Socket) -> () {
+    pub fn release_socket(&mut self, socket: Socket) {
         self.sockets.set_bit(socket.index.into(), true);
     }
 
diff --git a/src/network/mod.rs b/src/network/mod.rs
index 9899b9b..c920b0a 100644
--- a/src/network/mod.rs
+++ b/src/network/mod.rs
@@ -50,13 +50,13 @@ pub trait Network {
             current.subnet = settings.subnet;
         }
         if settings.mac != current.mac {
-            let mut address = settings.mac.address;
-            bus.write_frame(register::COMMON, register::common::MAC, &mut address)?;
+            let address = settings.mac.octets;
+            bus.write_frame(register::COMMON, register::common::MAC, &address)?;
             current.mac = settings.mac;
         }
         if settings.ip != current.ip {
-            let mut address = settings.ip.octets();
-            bus.write_frame(register::COMMON, register::common::IP, &mut address)?;
+            let address = settings.ip.octets();
+            bus.write_frame(register::COMMON, register::common::IP, &address)?;
             current.ip = settings.ip;
         }
         Ok(())
diff --git a/src/register.rs b/src/register.rs
index 0c16deb..8bd3ec6 100644
--- a/src/register.rs
+++ b/src/register.rs
@@ -1,3 +1,5 @@
+#![allow(clippy::unusual_byte_groupings)]
+
 pub const COMMON: u8 = 0;
 pub mod common {
     use bit_field::BitArray;
diff --git a/src/socket.rs b/src/socket.rs
index 03a5152..9eed73a 100644
--- a/src/socket.rs
+++ b/src/socket.rs
@@ -45,8 +45,8 @@ impl Socket {
         bus: &mut SpiBus,
         mode: socketn::Protocol,
     ) -> Result<(), SpiBus::Error> {
-        let mut mode = [mode as u8];
-        bus.write_frame(self.register(), socketn::MODE, &mut mode)?;
+        let mode = [mode as u8];
+        bus.write_frame(self.register(), socketn::MODE, &mode)?;
         Ok(())
     }
 
@@ -55,8 +55,8 @@ impl Socket {
         bus: &mut SpiBus,
         code: socketn::Interrupt,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = [code as u8];
-        bus.write_frame(self.register(), socketn::INTERRUPT, &mut data)?;
+        let data = [code as u8];
+        bus.write_frame(self.register(), socketn::INTERRUPT, &data)?;
         Ok(())
     }
 
@@ -75,8 +75,8 @@ impl Socket {
         bus: &mut SpiBus,
         port: u16,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = port.to_be_bytes();
-        bus.write_frame(self.register(), socketn::SOURCE_PORT, &mut data)?;
+        let data = port.to_be_bytes();
+        bus.write_frame(self.register(), socketn::SOURCE_PORT, &data)?;
         Ok(())
     }
 
@@ -85,8 +85,8 @@ impl Socket {
         bus: &mut SpiBus,
         ip: Ipv4Addr,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = ip.octets();
-        bus.write_frame(self.register(), socketn::DESTINATION_IP, &mut data)?;
+        let data = ip.octets();
+        bus.write_frame(self.register(), socketn::DESTINATION_IP, &data)?;
         Ok(())
     }
 
@@ -95,8 +95,8 @@ impl Socket {
         bus: &mut SpiBus,
         port: u16,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = port.to_be_bytes();
-        bus.write_frame(self.register(), socketn::DESTINATION_PORT, &mut data)?;
+        let data = port.to_be_bytes();
+        bus.write_frame(self.register(), socketn::DESTINATION_PORT, &data)?;
         Ok(())
     }
 
@@ -114,8 +114,8 @@ impl Socket {
         bus: &mut SpiBus,
         pointer: u16,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = pointer.to_be_bytes();
-        bus.write_frame(self.register(), socketn::TX_DATA_READ_POINTER, &mut data)?;
+        let data = pointer.to_be_bytes();
+        bus.write_frame(self.register(), socketn::TX_DATA_READ_POINTER, &data)?;
         Ok(())
     }
 
@@ -133,8 +133,8 @@ impl Socket {
         bus: &mut SpiBus,
         pointer: u16,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = pointer.to_be_bytes();
-        bus.write_frame(self.register(), socketn::TX_DATA_WRITE_POINTER, &mut data)?;
+        let data = pointer.to_be_bytes();
+        bus.write_frame(self.register(), socketn::TX_DATA_WRITE_POINTER, &data)?;
         Ok(())
     }
 
@@ -152,8 +152,8 @@ impl Socket {
         bus: &mut SpiBus,
         pointer: u16,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = pointer.to_be_bytes();
-        bus.write_frame(self.register(), socketn::RX_DATA_READ_POINTER, &mut data)?;
+        let data = pointer.to_be_bytes();
+        bus.write_frame(self.register(), socketn::RX_DATA_READ_POINTER, &data)?;
         Ok(())
     }
 
@@ -162,8 +162,8 @@ impl Socket {
         bus: &mut SpiBus,
         mask: u8,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = [mask];
-        bus.write_frame(self.register(), socketn::INTERRUPT_MASK, &mut data)?;
+        let data = [mask];
+        bus.write_frame(self.register(), socketn::INTERRUPT_MASK, &data)?;
         Ok(())
     }
 
@@ -172,8 +172,8 @@ impl Socket {
         bus: &mut SpiBus,
         command: socketn::Command,
     ) -> Result<(), SpiBus::Error> {
-        let mut data = [command as u8];
-        bus.write_frame(self.register(), socketn::COMMAND, &mut data)?;
+        let data = [command as u8];
+        bus.write_frame(self.register(), socketn::COMMAND, &data)?;
         Ok(())
     }
 
diff --git a/src/udp.rs b/src/udp.rs
index 2e024fa..068301d 100644
--- a/src/udp.rs
+++ b/src/udp.rs
@@ -121,7 +121,7 @@ impl UdpSocket {
         self.socket
             .set_rx_read_pointer(bus, tx_write_pointer)
             .and_then(|_| self.socket.command(bus, socketn::Command::Receive))?;
-        Ok((packet_size.into(), remote))
+        Ok((packet_size, remote))
     }
 
     fn close<SpiBus: ActiveBus>(
diff --git a/src/uninitialized_device.rs b/src/uninitialized_device.rs
index 1aa89fe..8786afe 100644
--- a/src/uninitialized_device.rs
+++ b/src/uninitialized_device.rs
@@ -20,7 +20,7 @@ pub enum InitializeError<SpiError> {
 
 impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
     pub fn new(bus: SpiBus) -> UninitializedDevice<SpiBus> {
-        UninitializedDevice { bus: bus }
+        UninitializedDevice { bus }
     }
 
     pub fn initialize(
@@ -65,16 +65,16 @@ impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
         self.assert_chip_version(0x4)?;
 
         // RESET
-        let mut mode = [0b10000000];
+        let mode = [0b10000000];
         self.bus
-            .write_frame(register::COMMON, register::common::MODE, &mut mode)
-            .map_err(|e| InitializeError::SpiError(e))?;
+            .write_frame(register::COMMON, register::common::MODE, &mode)
+            .map_err(InitializeError::SpiError)?;
 
         self.set_mode(mode_options)
-            .map_err(|e| InitializeError::SpiError(e))?;
+            .map_err(InitializeError::SpiError)?;
         network
             .refresh(&mut self.bus)
-            .map_err(|e| InitializeError::SpiError(e))?;
+            .map_err(InitializeError::SpiError)?;
         Ok(Device::new(self.bus, network))
     }
 
@@ -85,7 +85,7 @@ impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
         let mut version = [0];
         self.bus
             .read_frame(register::COMMON, register::common::VERSION, &mut version)
-            .map_err(|e| InitializeError::SpiError(e))?;
+            .map_err(InitializeError::SpiError)?;
         if version[0] != expected_version {
             Err(InitializeError::ChipNotConnected)
         } else {
@@ -100,7 +100,7 @@ impl<SpiBus: ActiveBus> UninitializedDevice<SpiBus> {
         mode[0] |= mode_options.connection_type as u8;
         mode[0] |= mode_options.arp_responses as u8;
         self.bus
-            .write_frame(register::COMMON, register::common::MODE, &mut mode)?;
+            .write_frame(register::COMMON, register::common::MODE, &mode)?;
         Ok(())
     }
 }