tuxmain/w5100-rs
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Added self to authors list, fixed Clippy lint errors

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This commit is contained in:
Jonah Dahlquist 2020-11-22 13:15:33 -08:00
commit 1cac758d5a
9 changed files with 59 additions and 55 deletions
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22
src/bus/four_wire.rs
View file

@ -1,3 +1,5 @@
#![allow(clippy::unusual_byte_groupings)]
use core::fmt;
use embedded_hal::digital::v2::OutputPin;
use embedded_hal::spi::FullDuplex;
@ -38,16 +40,12 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
let address_phase = address.to_be_bytes();
let control_phase = block << 3;
let data_phase = data;
self.cs
.set_low()
.map_err(|e| FourWireError::ChipSelectError(e))?;
self.cs.set_low().map_err(FourWireError::ChipSelectError)?;
Self::write_bytes(&mut self.spi, &address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, control_phase))
.and_then(|_| Self::read_bytes(&mut self.spi, data_phase))
.map_err(|e| FourWireError::SpiError(e))?;
self.cs
.set_high()
.map_err(|e| FourWireError::ChipSelectError(e))?;
.map_err(FourWireError::SpiError)?;
self.cs.set_high().map_err(FourWireError::ChipSelectError)?;
Ok(())
}
@ -55,16 +53,12 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
let address_phase = address.to_be_bytes();
let control_phase = block << 3 | WRITE_MODE_MASK;
let data_phase = data;
self.cs
.set_low()
.map_err(|e| FourWireError::ChipSelectError(e))?;
self.cs.set_low().map_err(FourWireError::ChipSelectError)?;
Self::write_bytes(&mut self.spi, &address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, control_phase))
.and_then(|_| Self::write_bytes(&mut self.spi, data_phase))
.map_err(|e| FourWireError::SpiError(e))?;
self.cs
.set_high()
.map_err(|e| FourWireError::ChipSelectError(e))?;
.map_err(FourWireError::SpiError)?;
self.cs.set_high().map_err(FourWireError::ChipSelectError)?;
Ok(())
}

16
src/bus/three_wire.rs
View file

@ -1,3 +1,5 @@
#![allow(clippy::unusual_byte_groupings)]
use core::fmt;
use embedded_hal::spi::FullDuplex;
@ -17,6 +19,12 @@ impl ThreeWire {
}
}
impl Default for ThreeWire {
fn default() -> Self {
Self::new()
}
}
impl Bus for ThreeWire {}
impl ThreeWire {
@ -53,7 +61,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
let mut data_phase = &mut data[..];
let mut last_length_written: u16;
while data_phase.len() > 0 {
while !data_phase.is_empty() {
if data_phase.len() >= 4 {
control_phase |= FIXED_DATA_LENGTH_MODE_4;
last_length_written = 4;
@ -74,7 +82,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
&mut data_phase[..last_length_written as usize],
)
})
.map_err(|e| ThreeWireError::SpiError(e))?;
.map_err(ThreeWireError::SpiError)?;
address += last_length_written;
data_phase = &mut data_phase[last_length_written as usize..];
@ -86,7 +94,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
let mut data_phase = &data[..];
let mut last_length_written: u16;
while data_phase.len() > 0 {
while !data_phase.is_empty() {
if data_phase.len() >= 4 {
control_phase |= FIXED_DATA_LENGTH_MODE_4;
last_length_written = 4;
@ -104,7 +112,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
.and_then(|_| {
Self::write_bytes(&mut self.spi, &data_phase[..last_length_written as usize])
})
.map_err(|e| ThreeWireError::SpiError(e))?;
.map_err(ThreeWireError::SpiError)?;
address += last_length_written;
data_phase = &data_phase[last_length_written as usize..];