tuxmain/w5100-rs
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Removed nb from areas where it's not necessary

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This commit is contained in:
Jonah Dahlquist 2020-07-26 17:14:30 -07:00
commit 074e01e3a0
9 changed files with 47 additions and 48 deletions
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6
src/bus/four_wire.rs
View file

@ -40,7 +40,7 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
address: u16, address: u16,
is_write: bool, is_write: bool,
data: &'a mut [u8], data: &'a mut [u8],
) -> Result<&'a mut [u8], nb::Error<Self::Error>> { ) -> Result<&'a mut [u8], Self::Error> {
let mut control_phase = block << 3; let mut control_phase = block << 3;
if is_write { if is_write {
control_phase |= WRITE_MODE_MASK; control_phase |= WRITE_MODE_MASK;
@ -52,9 +52,9 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
self.cs self.cs
.set_low() .set_low()
.map_err(|e| FourWireError::ChipSelectError(e))?; .map_err(|e| FourWireError::ChipSelectError(e))?;
block!(Self::transfer_bytes(&mut self.spi, &mut address_phase) Self::transfer_bytes(&mut self.spi, &mut address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase)) .and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase))
.and_then(|_| Self::transfer_bytes(&mut self.spi, data_phase))) .and_then(|_| Self::transfer_bytes(&mut self.spi, data_phase))
.map_err(|e| FourWireError::SpiError(e))?; .map_err(|e| FourWireError::SpiError(e))?;
self.cs self.cs
.set_high() .set_high()

3
src/bus/mod.rs
View file

@ -1,5 +1,4 @@
use embedded_hal::spi::FullDuplex; use embedded_hal::spi::FullDuplex;
use nb::Result;
mod four_wire; mod four_wire;
mod three_wire; mod three_wire;
@ -36,7 +35,7 @@ pub trait ActiveBus {
spi: &mut Spi, spi: &mut Spi,
byte: &'a mut u8, byte: &'a mut u8,
) -> Result<&'a mut u8, Spi::Error> { ) -> Result<&'a mut u8, Spi::Error> {
*byte = spi.send(*byte).and_then(|_| spi.read())?; *byte = block!(spi.send(*byte)).and_then(|_| block!(spi.read()))?;
Ok(byte) Ok(byte)
} }
} }

6
src/bus/three_wire.rs
View file

@ -49,7 +49,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
mut address: u16, mut address: u16,
is_write: bool, is_write: bool,
data: &'a mut [u8], data: &'a mut [u8],
) -> Result<&'a mut [u8], nb::Error<Self::Error>> { ) -> Result<&'a mut [u8], Self::Error> {
let mut control_phase = block << 3; let mut control_phase = block << 3;
if is_write { if is_write {
control_phase |= WRITE_MODE_MASK; control_phase |= WRITE_MODE_MASK;
@ -71,12 +71,12 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
let mut address_phase = [0u8; 2]; let mut address_phase = [0u8; 2];
BigEndian::write_u16(&mut address_phase, address); BigEndian::write_u16(&mut address_phase, address);
block!(Self::transfer_bytes(&mut self.spi, &mut address_phase) Self::transfer_bytes(&mut self.spi, &mut address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase)) .and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase))
.and_then(|_| Self::transfer_bytes( .and_then(|_| Self::transfer_bytes(
&mut self.spi, &mut self.spi,
&mut data_phase[..last_length_written as usize] &mut data_phase[..last_length_written as usize]
)))?; ))?;
address += last_length_written; address += last_length_written;
data_phase = &mut data_phase[last_length_written as usize..]; data_phase = &mut data_phase[last_length_written as usize..];

14
src/network/mod.rs
View file

@ -30,37 +30,37 @@ pub trait Network {
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
if settings.gateway != current.gateway { if settings.gateway != current.gateway {
let mut address = settings.gateway.address; let mut address = settings.gateway.address;
block!(bus.transfer_frame( bus.transfer_frame(
register::COMMON, register::COMMON,
register::common::GATEWAY, register::common::GATEWAY,
true, true,
&mut address &mut address
))?; )?;
current.gateway = settings.gateway; current.gateway = settings.gateway;
} }
if settings.subnet != current.subnet { if settings.subnet != current.subnet {
let mut address = settings.subnet.address; let mut address = settings.subnet.address;
block!(bus.transfer_frame( bus.transfer_frame(
register::COMMON, register::COMMON,
register::common::SUBNET_MASK, register::common::SUBNET_MASK,
true, true,
&mut address &mut address
))?; )?;
current.subnet = settings.subnet; current.subnet = settings.subnet;
} }
if settings.mac != current.mac { if settings.mac != current.mac {
let mut address = settings.mac.address; let mut address = settings.mac.address;
block!(bus.transfer_frame( bus.transfer_frame(
register::COMMON, register::COMMON,
register::common::MAC, register::common::MAC,
true, true,
&mut address &mut address
))?; )?;
current.mac = settings.mac; current.mac = settings.mac;
} }
if settings.ip != current.ip { if settings.ip != current.ip {
let mut address = settings.ip.address; let mut address = settings.ip.address;
block!(bus.transfer_frame(register::COMMON, register::common::IP, true, &mut address))?; bus.transfer_frame(register::COMMON, register::common::IP, true, &mut address)?;
current.ip = settings.ip; current.ip = settings.ip;
} }
Ok(()) Ok(())

42
src/socket/mod.rs
View file

@ -16,7 +16,7 @@ pub trait Socket {
mode: socketn::Protocol, mode: socketn::Protocol,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut mode = [mode as u8]; let mut mode = [mode as u8];
block!(bus.transfer_frame(self.register(), socketn::MODE, true, &mut mode))?; bus.transfer_frame(self.register(), socketn::MODE, true, &mut mode)?;
Ok(()) Ok(())
} }
@ -26,7 +26,7 @@ pub trait Socket {
code: socketn::Interrupt, code: socketn::Interrupt,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [code as u8]; let mut data = [code as u8];
block!(bus.transfer_frame(self.register(), socketn::INTERRUPT, true, &mut data))?; bus.transfer_frame(self.register(), socketn::INTERRUPT, true, &mut data)?;
Ok(()) Ok(())
} }
@ -37,7 +37,7 @@ pub trait Socket {
) -> Result<bool, SpiBus::Error> { ) -> Result<bool, SpiBus::Error> {
let mut data = [0u8]; let mut data = [0u8];
BigEndian::write_u16(&mut data, code as u16); BigEndian::write_u16(&mut data, code as u16);
block!(bus.transfer_frame(self.register(), socketn::INTERRUPT_MASK, true, &mut data))?; bus.transfer_frame(self.register(), socketn::INTERRUPT_MASK, true, &mut data)?;
Ok(data[0] & socketn::Interrupt::Receive as u8 != 0) Ok(data[0] & socketn::Interrupt::Receive as u8 != 0)
} }
@ -48,7 +48,7 @@ pub trait Socket {
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [0u8; 2]; let mut data = [0u8; 2];
BigEndian::write_u16(&mut data, port); BigEndian::write_u16(&mut data, port);
block!(bus.transfer_frame(self.register(), socketn::SOURCE_PORT, true, &mut data))?; bus.transfer_frame(self.register(), socketn::SOURCE_PORT, true, &mut data)?;
Ok(()) Ok(())
} }
@ -58,7 +58,7 @@ pub trait Socket {
ip: IpAddress, ip: IpAddress,
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = ip.address; let mut data = ip.address;
block!(bus.transfer_frame(self.register(), socketn::DESTINATION_IP, true, &mut data))?; bus.transfer_frame(self.register(), socketn::DESTINATION_IP, true, &mut data)?;
Ok(()) Ok(())
} }
@ -69,7 +69,7 @@ pub trait Socket {
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [0u8; 2]; let mut data = [0u8; 2];
BigEndian::write_u16(&mut data, port); BigEndian::write_u16(&mut data, port);
block!(bus.transfer_frame(self.register(), socketn::DESTINATION_PORT, true, &mut data))?; bus.transfer_frame(self.register(), socketn::DESTINATION_PORT, true, &mut data)?;
Ok(()) Ok(())
} }
@ -80,12 +80,12 @@ pub trait Socket {
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [0u8; 2]; let mut data = [0u8; 2];
BigEndian::write_u16(&mut data, pointer); BigEndian::write_u16(&mut data, pointer);
block!(bus.transfer_frame( bus.transfer_frame(
self.register(), self.register(),
socketn::TX_DATA_READ_POINTER, socketn::TX_DATA_READ_POINTER,
true, true,
&mut data &mut data
))?; )?;
Ok(()) Ok(())
} }
@ -96,12 +96,12 @@ pub trait Socket {
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [0u8; 2]; let mut data = [0u8; 2];
BigEndian::write_u16(&mut data, pointer); BigEndian::write_u16(&mut data, pointer);
block!(bus.transfer_frame( bus.transfer_frame(
self.register(), self.register(),
socketn::TX_DATA_WRITE_POINTER, socketn::TX_DATA_WRITE_POINTER,
true, true,
&mut data &mut data
))?; )?;
Ok(()) Ok(())
} }
@ -110,12 +110,12 @@ pub trait Socket {
bus: &mut SpiBus, bus: &mut SpiBus,
) -> Result<u16, SpiBus::Error> { ) -> Result<u16, SpiBus::Error> {
let mut data = [0u8; 2]; let mut data = [0u8; 2];
block!(bus.transfer_frame( bus.transfer_frame(
self.register(), self.register(),
socketn::RX_DATA_READ_POINTER, socketn::RX_DATA_READ_POINTER,
true, true,
&mut data &mut data
))?; )?;
Ok(BigEndian::read_u16(&data)) Ok(BigEndian::read_u16(&data))
} }
@ -126,12 +126,12 @@ pub trait Socket {
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [0u8; 2]; let mut data = [0u8; 2];
BigEndian::write_u16(&mut data, pointer); BigEndian::write_u16(&mut data, pointer);
block!(bus.transfer_frame( bus.transfer_frame(
self.register(), self.register(),
socketn::RX_DATA_READ_POINTER, socketn::RX_DATA_READ_POINTER,
true, true,
&mut data &mut data
))?; )?;
Ok(()) Ok(())
} }
@ -142,7 +142,7 @@ pub trait Socket {
) -> Result<(), SpiBus::Error> { ) -> Result<(), SpiBus::Error> {
let mut data = [0u8; 2]; let mut data = [0u8; 2];
BigEndian::write_u16(&mut data, command as u16); BigEndian::write_u16(&mut data, command as u16);
block!(bus.transfer_frame(self.register(), socketn::COMMAND, true, &mut data))?; bus.transfer_frame(self.register(), socketn::COMMAND, true, &mut data)?;
Ok(()) Ok(())
} }
@ -150,19 +150,19 @@ pub trait Socket {
loop { loop {
// Section 4.2 of datasheet, Sn_TX_FSR address docs indicate that read must be repeated until two sequential reads are stable // Section 4.2 of datasheet, Sn_TX_FSR address docs indicate that read must be repeated until two sequential reads are stable
let mut sample_0 = [0u8; 2]; let mut sample_0 = [0u8; 2];
block!(bus.transfer_frame( bus.transfer_frame(
self.register(), self.register(),
socketn::RECEIVED_SIZE, socketn::RECEIVED_SIZE,
false, false,
&mut sample_0 &mut sample_0
))?; )?;
let mut sample_1 = [0u8; 2]; let mut sample_1 = [0u8; 2];
block!(bus.transfer_frame( bus.transfer_frame(
self.register(), self.register(),
socketn::RECEIVED_SIZE, socketn::RECEIVED_SIZE,
false, false,
&mut sample_1 &mut sample_1
))?; )?;
if sample_0 == sample_1 && sample_0[0] >= 8 { if sample_0 == sample_1 && sample_0[0] >= 8 {
break Ok(BigEndian::read_u16(&sample_0)); break Ok(BigEndian::read_u16(&sample_0));
} }
@ -171,12 +171,12 @@ pub trait Socket {
fn dump_register<SpiBus: ActiveBus>(&self, bus: &mut SpiBus) -> [u8; 0x30] { fn dump_register<SpiBus: ActiveBus>(&self, bus: &mut SpiBus) -> [u8; 0x30] {
let mut register = [0u8; 0x30]; let mut register = [0u8; 0x30];
block!(bus.transfer_frame( bus.transfer_frame(
self.register(), self.register(),
0u16, 0u16,
false, false,
&mut register &mut register
)); );
register register
} }
} }

8
src/udp/incoming_packet.rs
View file

@ -32,12 +32,12 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network, SocketImpl: Socket>
.socket .socket
.get_rx_read_pointer(&mut udp_socket.w5500.bus)?; .get_rx_read_pointer(&mut udp_socket.w5500.bus)?;
let mut header = [0u8; 8]; let mut header = [0u8; 8];
block!(udp_socket.w5500.bus.transfer_frame( udp_socket.w5500.bus.transfer_frame(
udp_socket.socket.rx_buffer(), udp_socket.socket.rx_buffer(),
read_pointer, read_pointer,
false, false,
&mut header &mut header
))?; )?;
Ok(Self { Ok(Self {
udp_socket, udp_socket,
address: IpAddress::new(header[0], header[1], header[2], header[3]), address: IpAddress::new(header[0], header[1], header[2], header[3]),
@ -77,12 +77,12 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network, SocketImpl: Socket> Iterator
return None; return None;
} }
let mut buffer = [0u8]; let mut buffer = [0u8];
let result = block!(self.udp_socket.w5500.bus.transfer_frame( let result = self.udp_socket.w5500.bus.transfer_frame(
self.udp_socket.socket.rx_buffer(), self.udp_socket.socket.rx_buffer(),
self.read_pointer, self.read_pointer,
false, false,
&mut buffer &mut buffer
)); );
self.read_pointer += 1; self.read_pointer += 1;
// TODO handle looping back? // TODO handle looping back?
match result { match result {

4
src/udp/outgoing_packet.rs
View file

@ -34,12 +34,12 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network, SocketImpl: Socket>
} }
pub fn write(&mut self, mut data: &mut [u8]) -> Result<(), SpiBus::Error> { pub fn write(&mut self, mut data: &mut [u8]) -> Result<(), SpiBus::Error> {
block!(self.udp_socket.w5500.bus.transfer_frame( self.udp_socket.w5500.bus.transfer_frame(
self.udp_socket.socket.tx_buffer(), self.udp_socket.socket.tx_buffer(),
self.data_length, self.data_length,
true, true,
&mut data &mut data
))?; )?;
self.data_length += data.len() as u16; self.data_length += data.len() as u16;
Ok(()) Ok(())
} }

8
src/uninitialized_w5500.rs
View file

@ -85,12 +85,12 @@ impl<SpiBus: ActiveBus> UninitializedW5500<SpiBus> {
expected_version: u8, expected_version: u8,
) -> Result<(), InitializeError<SpiBus::Error>> { ) -> Result<(), InitializeError<SpiBus::Error>> {
let mut version = [0]; let mut version = [0];
block!(self.bus.transfer_frame( self.bus.transfer_frame(
register::COMMON, register::COMMON,
register::common::VERSION, register::common::VERSION,
false, false,
&mut version &mut version
)) )
.map_err(|e| InitializeError::SpiError(e))?; .map_err(|e| InitializeError::SpiError(e))?;
if version[0] != expected_version { if version[0] != expected_version {
Err(InitializeError::ChipNotConnected) Err(InitializeError::ChipNotConnected)
@ -105,9 +105,9 @@ impl<SpiBus: ActiveBus> UninitializedW5500<SpiBus> {
mode[0] |= mode_options.on_ping_request as u8; mode[0] |= mode_options.on_ping_request as u8;
mode[0] |= mode_options.connection_type as u8; mode[0] |= mode_options.connection_type as u8;
mode[0] |= mode_options.arp_responses as u8; mode[0] |= mode_options.arp_responses as u8;
block!(self self
.bus .bus
.transfer_frame(register::COMMON, register::common::MODE, true, &mut mode))?; .transfer_frame(register::COMMON, register::common::MODE, true, &mut mode)?;
Ok(()) Ok(())
} }
} }

4
src/w5500.rs
View file

@ -26,9 +26,9 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network> W5500<SpiBus, NetworkImpl> {
fn clear_mode(&mut self) -> Result<(), SpiBus::Error> { fn clear_mode(&mut self) -> Result<(), SpiBus::Error> {
// reset bit // reset bit
let mut mode = [0b10000000]; let mut mode = [0b10000000];
block!(self self
.bus .bus
.transfer_frame(register::COMMON, register::common::MODE, true, &mut mode))?; .transfer_frame(register::COMMON, register::common::MODE, true, &mut mode)?;
Ok(()) Ok(())
} }