diff --git a/src/bus/four_wire.rs b/src/bus/four_wire.rs
index 6300cc4..082bf32 100644
--- a/src/bus/four_wire.rs
+++ b/src/bus/four_wire.rs
@@ -40,7 +40,7 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
         address: u16,
         is_write: bool,
         data: &'a mut [u8],
-    ) -> Result<&'a mut [u8], nb::Error<Self::Error>> {
+    ) -> Result<&'a mut [u8], Self::Error> {
         let mut control_phase = block << 3;
         if is_write {
             control_phase |= WRITE_MODE_MASK;
@@ -52,9 +52,9 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
         self.cs
             .set_low()
             .map_err(|e| FourWireError::ChipSelectError(e))?;
-        block!(Self::transfer_bytes(&mut self.spi, &mut address_phase)
+        Self::transfer_bytes(&mut self.spi, &mut address_phase)
             .and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase))
-            .and_then(|_| Self::transfer_bytes(&mut self.spi, data_phase)))
+            .and_then(|_| Self::transfer_bytes(&mut self.spi, data_phase))
         .map_err(|e| FourWireError::SpiError(e))?;
         self.cs
             .set_high()
diff --git a/src/bus/mod.rs b/src/bus/mod.rs
index 45884b6..c80e13b 100644
--- a/src/bus/mod.rs
+++ b/src/bus/mod.rs
@@ -1,5 +1,4 @@
 use embedded_hal::spi::FullDuplex;
-use nb::Result;
 
 mod four_wire;
 mod three_wire;
@@ -36,7 +35,7 @@ pub trait ActiveBus {
         spi: &mut Spi,
         byte: &'a mut u8,
     ) -> Result<&'a mut u8, Spi::Error> {
-        *byte = spi.send(*byte).and_then(|_| spi.read())?;
+        *byte = block!(spi.send(*byte)).and_then(|_| block!(spi.read()))?;
         Ok(byte)
     }
 }
diff --git a/src/bus/three_wire.rs b/src/bus/three_wire.rs
index 38d77a8..8891797 100644
--- a/src/bus/three_wire.rs
+++ b/src/bus/three_wire.rs
@@ -49,7 +49,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
         mut address: u16,
         is_write: bool,
         data: &'a mut [u8],
-    ) -> Result<&'a mut [u8], nb::Error<Self::Error>> {
+    ) -> Result<&'a mut [u8], Self::Error> {
         let mut control_phase = block << 3;
         if is_write {
             control_phase |= WRITE_MODE_MASK;
@@ -71,12 +71,12 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
 
             let mut address_phase = [0u8; 2];
             BigEndian::write_u16(&mut address_phase, address);
-            block!(Self::transfer_bytes(&mut self.spi, &mut address_phase)
+            Self::transfer_bytes(&mut self.spi, &mut address_phase)
                 .and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase))
                 .and_then(|_| Self::transfer_bytes(
                     &mut self.spi,
                     &mut data_phase[..last_length_written as usize]
-                )))?;
+                ))?;
 
             address += last_length_written;
             data_phase = &mut data_phase[last_length_written as usize..];
diff --git a/src/network/mod.rs b/src/network/mod.rs
index 4d0f331..19ed9b5 100644
--- a/src/network/mod.rs
+++ b/src/network/mod.rs
@@ -30,37 +30,37 @@ pub trait Network {
     ) -> Result<(), SpiBus::Error> {
         if settings.gateway != current.gateway {
             let mut address = settings.gateway.address;
-            block!(bus.transfer_frame(
+            bus.transfer_frame(
                 register::COMMON,
                 register::common::GATEWAY,
                 true,
                 &mut address
-            ))?;
+            )?;
             current.gateway = settings.gateway;
         }
         if settings.subnet != current.subnet {
             let mut address = settings.subnet.address;
-            block!(bus.transfer_frame(
+            bus.transfer_frame(
                 register::COMMON,
                 register::common::SUBNET_MASK,
                 true,
                 &mut address
-            ))?;
+            )?;
             current.subnet = settings.subnet;
         }
         if settings.mac != current.mac {
             let mut address = settings.mac.address;
-            block!(bus.transfer_frame(
+            bus.transfer_frame(
                 register::COMMON,
                 register::common::MAC,
                 true,
                 &mut address
-            ))?;
+            )?;
             current.mac = settings.mac;
         }
         if settings.ip != current.ip {
             let mut address = settings.ip.address;
-            block!(bus.transfer_frame(register::COMMON, register::common::IP, true, &mut address))?;
+            bus.transfer_frame(register::COMMON, register::common::IP, true, &mut address)?;
             current.ip = settings.ip;
         }
         Ok(())
diff --git a/src/socket/mod.rs b/src/socket/mod.rs
index c54c33e..10b6786 100644
--- a/src/socket/mod.rs
+++ b/src/socket/mod.rs
@@ -16,7 +16,7 @@ pub trait Socket {
         mode: socketn::Protocol,
     ) -> Result<(), SpiBus::Error> {
         let mut mode = [mode as u8];
-        block!(bus.transfer_frame(self.register(), socketn::MODE, true, &mut mode))?;
+        bus.transfer_frame(self.register(), socketn::MODE, true, &mut mode)?;
         Ok(())
     }
 
@@ -26,7 +26,7 @@ pub trait Socket {
         code: socketn::Interrupt,
     ) -> Result<(), SpiBus::Error> {
         let mut data = [code as u8];
-        block!(bus.transfer_frame(self.register(), socketn::INTERRUPT, true, &mut data))?;
+        bus.transfer_frame(self.register(), socketn::INTERRUPT, true, &mut data)?;
         Ok(())
     }
 
@@ -37,7 +37,7 @@ pub trait Socket {
     ) -> Result<bool, SpiBus::Error> {
         let mut data = [0u8];
         BigEndian::write_u16(&mut data, code as u16);
-        block!(bus.transfer_frame(self.register(), socketn::INTERRUPT_MASK, true, &mut data))?;
+        bus.transfer_frame(self.register(), socketn::INTERRUPT_MASK, true, &mut data)?;
         Ok(data[0] & socketn::Interrupt::Receive as u8 != 0)
     }
 
@@ -48,7 +48,7 @@ pub trait Socket {
     ) -> Result<(), SpiBus::Error> {
         let mut data = [0u8; 2];
         BigEndian::write_u16(&mut data, port);
-        block!(bus.transfer_frame(self.register(), socketn::SOURCE_PORT, true, &mut data))?;
+        bus.transfer_frame(self.register(), socketn::SOURCE_PORT, true, &mut data)?;
         Ok(())
     }
 
@@ -58,7 +58,7 @@ pub trait Socket {
         ip: IpAddress,
     ) -> Result<(), SpiBus::Error> {
         let mut data = ip.address;
-        block!(bus.transfer_frame(self.register(), socketn::DESTINATION_IP, true, &mut data))?;
+        bus.transfer_frame(self.register(), socketn::DESTINATION_IP, true, &mut data)?;
         Ok(())
     }
 
@@ -69,7 +69,7 @@ pub trait Socket {
     ) -> Result<(), SpiBus::Error> {
         let mut data = [0u8; 2];
         BigEndian::write_u16(&mut data, port);
-        block!(bus.transfer_frame(self.register(), socketn::DESTINATION_PORT, true, &mut data))?;
+        bus.transfer_frame(self.register(), socketn::DESTINATION_PORT, true, &mut data)?;
         Ok(())
     }
 
@@ -80,12 +80,12 @@ pub trait Socket {
     ) -> Result<(), SpiBus::Error> {
         let mut data = [0u8; 2];
         BigEndian::write_u16(&mut data, pointer);
-        block!(bus.transfer_frame(
+        bus.transfer_frame(
             self.register(),
             socketn::TX_DATA_READ_POINTER,
             true,
             &mut data
-        ))?;
+        )?;
         Ok(())
     }
 
@@ -96,12 +96,12 @@ pub trait Socket {
     ) -> Result<(), SpiBus::Error> {
         let mut data = [0u8; 2];
         BigEndian::write_u16(&mut data, pointer);
-        block!(bus.transfer_frame(
+        bus.transfer_frame(
             self.register(),
             socketn::TX_DATA_WRITE_POINTER,
             true,
             &mut data
-        ))?;
+        )?;
         Ok(())
     }
 
@@ -110,12 +110,12 @@ pub trait Socket {
         bus: &mut SpiBus,
     ) -> Result<u16, SpiBus::Error> {
         let mut data = [0u8; 2];
-        block!(bus.transfer_frame(
+        bus.transfer_frame(
             self.register(),
             socketn::RX_DATA_READ_POINTER,
             true,
             &mut data
-        ))?;
+        )?;
         Ok(BigEndian::read_u16(&data))
     }
 
@@ -126,12 +126,12 @@ pub trait Socket {
     ) -> Result<(), SpiBus::Error> {
         let mut data = [0u8; 2];
         BigEndian::write_u16(&mut data, pointer);
-        block!(bus.transfer_frame(
+        bus.transfer_frame(
             self.register(),
             socketn::RX_DATA_READ_POINTER,
             true,
             &mut data
-        ))?;
+        )?;
         Ok(())
     }
 
@@ -142,7 +142,7 @@ pub trait Socket {
     ) -> Result<(), SpiBus::Error> {
         let mut data = [0u8; 2];
         BigEndian::write_u16(&mut data, command as u16);
-        block!(bus.transfer_frame(self.register(), socketn::COMMAND, true, &mut data))?;
+        bus.transfer_frame(self.register(), socketn::COMMAND, true, &mut data)?;
         Ok(())
     }
 
@@ -150,19 +150,19 @@ pub trait Socket {
         loop {
             // Section 4.2 of datasheet, Sn_TX_FSR address docs indicate that read must be repeated until two sequential reads are stable
             let mut sample_0 = [0u8; 2];
-            block!(bus.transfer_frame(
+            bus.transfer_frame(
                 self.register(),
                 socketn::RECEIVED_SIZE,
                 false,
                 &mut sample_0
-            ))?;
+            )?;
             let mut sample_1 = [0u8; 2];
-            block!(bus.transfer_frame(
+            bus.transfer_frame(
                 self.register(),
                 socketn::RECEIVED_SIZE,
                 false,
                 &mut sample_1
-            ))?;
+            )?;
             if sample_0 == sample_1 && sample_0[0] >= 8 {
                 break Ok(BigEndian::read_u16(&sample_0));
             }
@@ -171,12 +171,12 @@ pub trait Socket {
 
     fn dump_register<SpiBus: ActiveBus>(&self, bus: &mut SpiBus) -> [u8; 0x30] {
         let mut register = [0u8; 0x30];
-        block!(bus.transfer_frame(
+        bus.transfer_frame(
             self.register(),
             0u16,
             false,
             &mut register
-        ));
+        );
         register
     }
 }
diff --git a/src/udp/incoming_packet.rs b/src/udp/incoming_packet.rs
index bdb2df0..ccf8866 100644
--- a/src/udp/incoming_packet.rs
+++ b/src/udp/incoming_packet.rs
@@ -32,12 +32,12 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network, SocketImpl: Socket>
             .socket
             .get_rx_read_pointer(&mut udp_socket.w5500.bus)?;
         let mut header = [0u8; 8];
-        block!(udp_socket.w5500.bus.transfer_frame(
+        udp_socket.w5500.bus.transfer_frame(
             udp_socket.socket.rx_buffer(),
             read_pointer,
             false,
             &mut header
-        ))?;
+        )?;
         Ok(Self {
             udp_socket,
             address: IpAddress::new(header[0], header[1], header[2], header[3]),
@@ -77,12 +77,12 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network, SocketImpl: Socket> Iterator
             return None;
         }
         let mut buffer = [0u8];
-        let result = block!(self.udp_socket.w5500.bus.transfer_frame(
+        let result = self.udp_socket.w5500.bus.transfer_frame(
             self.udp_socket.socket.rx_buffer(),
             self.read_pointer,
             false,
             &mut buffer
-        ));
+        );
         self.read_pointer += 1;
         // TODO handle looping back?
         match result {
diff --git a/src/udp/outgoing_packet.rs b/src/udp/outgoing_packet.rs
index 34ec621..8ebd612 100644
--- a/src/udp/outgoing_packet.rs
+++ b/src/udp/outgoing_packet.rs
@@ -34,12 +34,12 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network, SocketImpl: Socket>
     }
 
     pub fn write(&mut self, mut data: &mut [u8]) -> Result<(), SpiBus::Error> {
-        block!(self.udp_socket.w5500.bus.transfer_frame(
+        self.udp_socket.w5500.bus.transfer_frame(
             self.udp_socket.socket.tx_buffer(),
             self.data_length,
             true,
             &mut data
-        ))?;
+        )?;
         self.data_length += data.len() as u16;
         Ok(())
     }
diff --git a/src/uninitialized_w5500.rs b/src/uninitialized_w5500.rs
index 2cda59e..cd5159f 100644
--- a/src/uninitialized_w5500.rs
+++ b/src/uninitialized_w5500.rs
@@ -85,12 +85,12 @@ impl<SpiBus: ActiveBus> UninitializedW5500<SpiBus> {
         expected_version: u8,
     ) -> Result<(), InitializeError<SpiBus::Error>> {
         let mut version = [0];
-        block!(self.bus.transfer_frame(
+        self.bus.transfer_frame(
             register::COMMON,
             register::common::VERSION,
             false,
             &mut version
-        ))
+        )
         .map_err(|e| InitializeError::SpiError(e))?;
         if version[0] != expected_version {
             Err(InitializeError::ChipNotConnected)
@@ -105,9 +105,9 @@ impl<SpiBus: ActiveBus> UninitializedW5500<SpiBus> {
         mode[0] |= mode_options.on_ping_request as u8;
         mode[0] |= mode_options.connection_type as u8;
         mode[0] |= mode_options.arp_responses as u8;
-        block!(self
+        self
             .bus
-            .transfer_frame(register::COMMON, register::common::MODE, true, &mut mode))?;
+            .transfer_frame(register::COMMON, register::common::MODE, true, &mut mode)?;
         Ok(())
     }
 }
diff --git a/src/w5500.rs b/src/w5500.rs
index 09286e0..7bce02a 100644
--- a/src/w5500.rs
+++ b/src/w5500.rs
@@ -26,9 +26,9 @@ impl<SpiBus: ActiveBus, NetworkImpl: Network> W5500<SpiBus, NetworkImpl> {
     fn clear_mode(&mut self) -> Result<(), SpiBus::Error> {
         // reset bit
         let mut mode = [0b10000000];
-        block!(self
+        self
             .bus
-            .transfer_frame(register::COMMON, register::common::MODE, true, &mut mode))?;
+            .transfer_frame(register::COMMON, register::common::MODE, true, &mut mode)?;
         Ok(())
     }