tuxmain/w5100-rs
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Removed nb from areas where it's not necessary

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This commit is contained in:
Jonah Dahlquist 2020-07-26 17:14:30 -07:00
commit 074e01e3a0
9 changed files with 47 additions and 48 deletions
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6
src/bus/four_wire.rs
View file

@ -40,7 +40,7 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
address: u16,
is_write: bool,
data: &'a mut [u8],
) -> Result<&'a mut [u8], nb::Error<Self::Error>> {
) -> Result<&'a mut [u8], Self::Error> {
let mut control_phase = block << 3;
if is_write {
control_phase |= WRITE_MODE_MASK;
@ -52,9 +52,9 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
self.cs
.set_low()
.map_err(|e| FourWireError::ChipSelectError(e))?;
block!(Self::transfer_bytes(&mut self.spi, &mut address_phase)
Self::transfer_bytes(&mut self.spi, &mut address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase))
.and_then(|_| Self::transfer_bytes(&mut self.spi, data_phase)))
.and_then(|_| Self::transfer_bytes(&mut self.spi, data_phase))
.map_err(|e| FourWireError::SpiError(e))?;
self.cs
.set_high()

3
src/bus/mod.rs
View file

@ -1,5 +1,4 @@
use embedded_hal::spi::FullDuplex;
use nb::Result;
mod four_wire;
mod three_wire;
@ -36,7 +35,7 @@ pub trait ActiveBus {
spi: &mut Spi,
byte: &'a mut u8,
) -> Result<&'a mut u8, Spi::Error> {
*byte = spi.send(*byte).and_then(|_| spi.read())?;
*byte = block!(spi.send(*byte)).and_then(|_| block!(spi.read()))?;
Ok(byte)
}
}

6
src/bus/three_wire.rs
View file

@ -49,7 +49,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
mut address: u16,
is_write: bool,
data: &'a mut [u8],
) -> Result<&'a mut [u8], nb::Error<Self::Error>> {
) -> Result<&'a mut [u8], Self::Error> {
let mut control_phase = block << 3;
if is_write {
control_phase |= WRITE_MODE_MASK;
@ -71,12 +71,12 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
let mut address_phase = [0u8; 2];
BigEndian::write_u16(&mut address_phase, address);
block!(Self::transfer_bytes(&mut self.spi, &mut address_phase)
Self::transfer_bytes(&mut self.spi, &mut address_phase)
.and_then(|_| Self::transfer_byte(&mut self.spi, &mut control_phase))
.and_then(|_| Self::transfer_bytes(
&mut self.spi,
&mut data_phase[..last_length_written as usize]
)))?;
))?;
address += last_length_written;
data_phase = &mut data_phase[last_length_written as usize..];