Be able to IP, Subnet, Gateway and Mac; and send udp packets
This commit is contained in:
Michael Watzko
commit
f28b948dac
4 changed files with 532 additions and 0 deletions
3
.gitignore
vendored
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3
.gitignore
vendored
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@ -0,0 +1,3 @@
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/target
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**/*.rs.bk
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31
Cargo.lock
generated
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31
Cargo.lock
generated
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@ -0,0 +1,31 @@
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[[package]]
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name = "byteorder"
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version = "1.2.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "embedded-hal"
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version = "0.1.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"nb 0.1.1 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "nb"
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version = "0.1.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "w5500"
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version = "0.1.0"
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dependencies = [
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"byteorder 1.2.1 (registry+https://github.com/rust-lang/crates.io-index)",
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"embedded-hal 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"nb 0.1.1 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[metadata]
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"checksum byteorder 1.2.1 (registry+https://github.com/rust-lang/crates.io-index)" = "652805b7e73fada9d85e9a6682a4abd490cb52d96aeecc12e33a0de34dfd0d23"
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"checksum embedded-hal 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)" = "684b1fa3196f78342296d04edc2a6e5d053729d1b64a819dcb072810d706e267"
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"checksum nb 0.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "69f380b5fe9fab8c0d7a6a99cda23e2cc0463bedb2cbc3aada0813b98496ecdc"
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9
Cargo.toml
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9
Cargo.toml
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@ -0,0 +1,9 @@
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[package]
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name = "w5500"
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version = "0.1.0"
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authors = ["Michael Watzko <michael@watzko.de>"]
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[dependencies]
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byteorder = { version = "1.2.1", default-features = false }
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embedded-hal = "0.1.2"
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nb = "0.1.1"
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489
src/lib.rs
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489
src/lib.rs
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@ -0,0 +1,489 @@
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#![no_std]
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#![allow(unused)]
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#![feature(const_fn)]
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extern crate byteorder;
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extern crate embedded_hal as hal;
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#[macro_use(block)]
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extern crate nb;
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use hal::digital::OutputPin;
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use hal::spi::FullDuplex;
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use byteorder::ByteOrder;
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use byteorder::BigEndian;
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const COMMAND_READ : u8 = 0x00 << 2;
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const COMMAND_WRITE : u8 = 0x01 << 2;
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const VARIABLE_DATA_LENGTH : u8 = 0b_00;
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const FIXED_DATA_LENGTH_1_BYTE : u8 = 0b_01;
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const FIXED_DATA_LENGTH_2_BYTES : u8 = 0b_10;
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const FIXED_DATA_LENGTH_4_BYTES : u8 = 0b_11;
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#[derive(Copy, Clone, PartialOrd, PartialEq, Default, Debug)]
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pub struct IpAddress {
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address: [u8; 4]
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}
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impl IpAddress {
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pub fn new(a0: u8, a1: u8, a2: u8, a3: u8) -> IpAddress {
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IpAddress {
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address: [a0, a1, a2, a3]
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}
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}
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}
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impl ::core::fmt::Display for IpAddress {
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fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
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write!(f, "{}.{}.{}.{}",
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self.address[0],
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self.address[1],
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self.address[2],
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self.address[3],
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)
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}
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}
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#[derive(Copy, Clone, PartialOrd, PartialEq, Default, Debug)]
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pub struct MacAddress {
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address: [u8; 6]
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}
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impl MacAddress {
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pub fn new(a0: u8, a1: u8, a2: u8, a3: u8, a4: u8, a5: u8) -> MacAddress {
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MacAddress {
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address: [a0, a1, a2, a3, a4, a5]
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}
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}
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}
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impl ::core::fmt::Display for MacAddress {
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fn fmt(&self, f: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
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write!(f, "{:02x}:{:02x}:{:02x}:{:02x}:{:02x}:{:02x}",
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self.address[0],
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self.address[1],
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self.address[2],
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self.address[3],
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self.address[4],
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self.address[5],
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)
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}
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}
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pub struct W5500<E, S: FullDuplex<u8, Error=E> + Sized, O: OutputPin> {
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spi: S,
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cs: O,
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}
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impl<E, S: FullDuplex<u8, Error=E> + Sized, O: OutputPin> W5500<E, S, O> {
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pub fn new(spi: S, cs: O) -> Result<W5500<E, S, O>, E> {
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W5500 {
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spi,
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cs,
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}.init()
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}
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fn init(mut self) -> Result<Self, E> {
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self.reset()?;
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self.set_mode(false, false, false, false)?;
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self.set_mac(&MacAddress::new(0x00, 0x08, 0xDC, 0x01, 0x02, 0x03))?;
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self.set_ip(&IpAddress::new(192, 168, 3, 222))?;
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self.set_subnet(&IpAddress::new(255, 255, 255, 0))?;
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self.set_gateway(&IpAddress::new(192, 168, 3, 1))?;
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// socket 0 with udp
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self.write_to(
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Register::Socket0Register(0x00_00),
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&[
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0b0000_0010, // UDP
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0x01 // OPEN / initialize
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]
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);
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self.write_to(
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Register::Socket0Register(0x00_04),
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&[
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0, 50, // local port u16
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // destination mac
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192, 168, 3, 55, // target IP
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0x14, 0xEA, // destination port (5354)
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]
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)?;
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self.write_to(
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Register::Socket0Register(0x00_01),
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&[
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0x20 // SEND
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]
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)?;
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Ok(self)
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}
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pub fn reset(&mut self) -> Result<(), E> {
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self.write_to(
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Register::CommonRegister(0x00_00_u16),
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&[
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0b1000_0000, // Mode Register (force reset)
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]
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)
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}
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pub fn set_mode(&mut self, wol: bool, ping_block: bool, ppoe: bool, force_arp: bool) -> Result<(), E> {
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let mut mode = 0x00;
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if wol {
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mode |= (1 << 5);
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}
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if ping_block {
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mode |= (1 << 4);
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}
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if ppoe {
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mode |= (1 << 3);
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}
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if force_arp {
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mode |= (1 << 1);
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}
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self.write_to(
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Register::CommonRegister(0x00_00_u16),
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&[mode]
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)
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}
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pub fn set_gateway(&mut self, gateway: &IpAddress) -> Result<(), E> {
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self.write_to(
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Register::CommonRegister(0x00_01_u16),
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&gateway.address
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)
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}
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pub fn set_subnet(&mut self, subnet: &IpAddress) -> Result<(), E> {
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self.write_to(
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Register::CommonRegister(0x00_05_u16),
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&subnet.address
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)
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}
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pub fn set_mac(&mut self, mac: &MacAddress) -> Result<(), E> {
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self.write_to(
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Register::CommonRegister(0x00_09_u16),
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&mac.address
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)
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}
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pub fn get_mac(&mut self) -> Result<MacAddress, E> {
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let mut mac = MacAddress::default();
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self.read_from(
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Register::CommonRegister(0x00_09_u16),
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&mut mac.address
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)?;
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Ok(mac)
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}
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pub fn set_ip(&mut self, ip: &IpAddress) -> Result<(), E> {
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self.write_to(
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Register::CommonRegister(0x00_0F_u16),
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&ip.address
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)
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}
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pub fn send_udp(&mut self, socket: Socket, local_port: u16, host: &IpAddress, host_port: u16, data: &[u8]) -> Result<(), E> {
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// TODO not always socket 0
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// TODO check if in use
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self.write_to(
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socket.register_at(0x00_00),
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&[
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0b0000_0010, // UDP
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0x01 // OPEN / initialize
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]
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);
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{
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let local_port = u16_to_be_bytes(local_port);
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let host_port = u16_to_be_bytes(host_port);
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self.write_to(
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socket.register_at(0x00_04),
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&[
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local_port[0], local_port[1], // local port u16
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // destination mac
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host.address[0], host.address[1], host.address[2], host.address[3], // target IP
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host_port[0], host_port[1], // destination port (5354)
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]
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)?;
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}
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let data_length = data.len() as u16;
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{
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let data_length = u16_to_be_bytes(data_length);
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self.write_to(
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socket.register_at(0x00_22),
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&[
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0x00, 0x00,
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data_length[0], data_length[1],
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]
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);
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}
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self.write_to(
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socket.tx_register_at(0x00_00),
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&data[..data_length as usize]
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);
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self.write_to(
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socket.register_at(0x00_01),
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&[
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0x20 // SEND
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]
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)
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}
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pub fn read_from(&mut self, register: Register, target: &mut [u8]) -> Result<(), E> {
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self.chip_select();
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let mut request = [0_u8, 0_u8, register.control_byte() | COMMAND_READ | VARIABLE_DATA_LENGTH];
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BigEndian::write_u16(&mut request[..2], register.address());
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let result = self
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.write_bytes(&request)
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.and_then(|_| self.read_bytes(target));
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self.chip_deselect();
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result
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}
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pub fn write_to(&mut self, register: Register, data: &[u8]) -> Result<(), E> {
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self.chip_select();
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let mut request = [0_u8, 0_u8, register.control_byte() | COMMAND_WRITE | VARIABLE_DATA_LENGTH];
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BigEndian::write_u16(&mut request[..2], register.address());
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let result = self
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.write_bytes(&request)
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.and_then(|_| self.write_bytes(data));
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self.chip_deselect();
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result
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}
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fn read_bytes(&mut self, bytes: &mut [u8]) -> Result<(), E> {
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for i in 0..bytes.len() {
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bytes[i] = self.read()?;
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}
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Ok(())
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}
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fn read(&mut self) -> Result<u8, E> {
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block!(self.spi.send(0x00))?;
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let result = block!(self.spi.read());
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result
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}
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fn write_bytes(&mut self, bytes: &[u8]) -> Result<(), E> {
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for b in bytes {
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self.write(*b)?;
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}
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Ok(())
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}
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fn write(&mut self, byte: u8) -> Result<(), E> {
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block!(self.spi.send(byte))?;
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block!(self.spi.read())?;
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Ok(())
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}
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fn chip_select(&mut self) {
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self.cs.set_low()
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}
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fn chip_deselect(&mut self) {
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self.cs.set_high()
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}
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}
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fn u16_to_be_bytes(u16: u16) -> [u8; 2] {
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let mut bytes = [0u8; 2];
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BigEndian::write_u16(&mut bytes, u16);
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bytes
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}
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#[derive(Copy, Clone, PartialEq, PartialOrd, Debug)]
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pub enum Socket {
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Socket0,
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Socket1,
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Socket2,
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Socket3,
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Socket4,
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Socket5,
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Socket6,
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Socket7,
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}
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impl Socket {
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fn tx_register_at(&self, address: u16) -> Register {
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match *self {
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Socket::Socket0 => Register::Socket0TxBuffer(address),
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Socket::Socket1 => Register::Socket1TxBuffer(address),
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Socket::Socket2 => Register::Socket2TxBuffer(address),
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Socket::Socket3 => Register::Socket3TxBuffer(address),
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Socket::Socket4 => Register::Socket4TxBuffer(address),
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Socket::Socket5 => Register::Socket5TxBuffer(address),
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Socket::Socket6 => Register::Socket6TxBuffer(address),
|
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Socket::Socket7 => Register::Socket7TxBuffer(address),
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}
|
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}
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fn rx_register_at(&self, address: u16) -> Register {
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match *self {
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Socket::Socket0 => Register::Socket0RxBuffer(address),
|
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Socket::Socket1 => Register::Socket1RxBuffer(address),
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Socket::Socket2 => Register::Socket2RxBuffer(address),
|
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Socket::Socket3 => Register::Socket3RxBuffer(address),
|
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Socket::Socket4 => Register::Socket4RxBuffer(address),
|
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Socket::Socket5 => Register::Socket5RxBuffer(address),
|
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Socket::Socket6 => Register::Socket6RxBuffer(address),
|
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Socket::Socket7 => Register::Socket7RxBuffer(address),
|
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}
|
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}
|
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|
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fn register_at(&self, address: u16) -> Register {
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match *self {
|
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Socket::Socket0 => Register::Socket0Register(address),
|
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Socket::Socket1 => Register::Socket1Register(address),
|
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Socket::Socket2 => Register::Socket2Register(address),
|
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Socket::Socket3 => Register::Socket3Register(address),
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Socket::Socket4 => Register::Socket4Register(address),
|
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Socket::Socket5 => Register::Socket5Register(address),
|
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Socket::Socket6 => Register::Socket6Register(address),
|
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Socket::Socket7 => Register::Socket7Register(address),
|
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}
|
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}
|
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}
|
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|
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#[derive(Copy, Clone, PartialEq, Debug)]
|
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pub enum Register {
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CommonRegister(u16),
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|
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Socket0Register(u16),
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Socket0TxBuffer(u16),
|
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Socket0RxBuffer(u16),
|
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|
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Socket1Register(u16),
|
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Socket1TxBuffer(u16),
|
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Socket1RxBuffer(u16),
|
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|
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Socket2Register(u16),
|
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Socket2TxBuffer(u16),
|
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Socket2RxBuffer(u16),
|
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|
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Socket3Register(u16),
|
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Socket3TxBuffer(u16),
|
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Socket3RxBuffer(u16),
|
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|
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Socket4Register(u16),
|
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Socket4TxBuffer(u16),
|
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Socket4RxBuffer(u16),
|
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|
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Socket5Register(u16),
|
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Socket5TxBuffer(u16),
|
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Socket5RxBuffer(u16),
|
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|
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Socket6Register(u16),
|
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Socket6TxBuffer(u16),
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Socket6RxBuffer(u16),
|
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|
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Socket7Register(u16),
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Socket7TxBuffer(u16),
|
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Socket7RxBuffer(u16),
|
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}
|
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|
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impl Register {
|
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fn control_byte(&self) -> u8 {
|
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match *self {
|
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Register::CommonRegister(_) => 0b00000_000,
|
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|
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Register::Socket0Register(_) => 0b00001_000,
|
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Register::Socket0TxBuffer(_) => 0b00010_000,
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Register::Socket0RxBuffer(_) => 0b00011_000,
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|
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Register::Socket1Register(_) => 0b00101_000,
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Register::Socket1TxBuffer(_) => 0b00110_000,
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Register::Socket1RxBuffer(_) => 0b00111_000,
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|
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Register::Socket2Register(_) => 0b01001_000,
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Register::Socket2TxBuffer(_) => 0b01010_000,
|
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Register::Socket2RxBuffer(_) => 0b01011_000,
|
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|
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Register::Socket3Register(_) => 0b01101_000,
|
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Register::Socket3TxBuffer(_) => 0b01110_000,
|
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Register::Socket3RxBuffer(_) => 0b01111_000,
|
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|
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Register::Socket4Register(_) => 0b10001_000,
|
||||
Register::Socket4TxBuffer(_) => 0b10010_000,
|
||||
Register::Socket4RxBuffer(_) => 0b10011_000,
|
||||
|
||||
Register::Socket5Register(_) => 0b10101_000,
|
||||
Register::Socket5TxBuffer(_) => 0b10110_000,
|
||||
Register::Socket5RxBuffer(_) => 0b10111_000,
|
||||
|
||||
Register::Socket6Register(_) => 0b11001_000,
|
||||
Register::Socket6TxBuffer(_) => 0b11010_000,
|
||||
Register::Socket6RxBuffer(_) => 0b11011_000,
|
||||
|
||||
Register::Socket7Register(_) => 0b11101_000,
|
||||
Register::Socket7TxBuffer(_) => 0b11110_000,
|
||||
Register::Socket7RxBuffer(_) => 0b11111_000,
|
||||
}
|
||||
}
|
||||
|
||||
fn address(&self) -> u16 {
|
||||
match *self {
|
||||
Register::CommonRegister(address) => address,
|
||||
|
||||
Register::Socket0Register(address) => address,
|
||||
Register::Socket0TxBuffer(address) => address,
|
||||
Register::Socket0RxBuffer(address) => address,
|
||||
|
||||
Register::Socket1Register(address) => address,
|
||||
Register::Socket1TxBuffer(address) => address,
|
||||
Register::Socket1RxBuffer(address) => address,
|
||||
|
||||
Register::Socket2Register(address) => address,
|
||||
Register::Socket2TxBuffer(address) => address,
|
||||
Register::Socket2RxBuffer(address) => address,
|
||||
|
||||
Register::Socket3Register(address) => address,
|
||||
Register::Socket3TxBuffer(address) => address,
|
||||
Register::Socket3RxBuffer(address) => address,
|
||||
|
||||
Register::Socket4Register(address) => address,
|
||||
Register::Socket4TxBuffer(address) => address,
|
||||
Register::Socket4RxBuffer(address) => address,
|
||||
|
||||
Register::Socket5Register(address) => address,
|
||||
Register::Socket5TxBuffer(address) => address,
|
||||
Register::Socket5RxBuffer(address) => address,
|
||||
|
||||
Register::Socket6Register(address) => address,
|
||||
Register::Socket6TxBuffer(address) => address,
|
||||
Register::Socket6RxBuffer(address) => address,
|
||||
|
||||
Register::Socket7Register(address) => address,
|
||||
Register::Socket7TxBuffer(address) => address,
|
||||
Register::Socket7RxBuffer(address) => address,
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue