tuxmain/w5100-rs
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Fixed bug in bitmasking

Browse source
This commit is contained in:
Jonah Dahlquist 2019-08-09 17:53:10 -05:00 • committed by Jonah Dahlquist
commit e74f7f401b
2 changed files with 10 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/bus/four_wire.rs
View file

@ -4,8 +4,7 @@ use embedded_hal::spi::FullDuplex;
use crate::bus::{ActiveBus, Bus}; use crate::bus::{ActiveBus, Bus};
const WRITE_MODE_MASK: u8 = 0b11111_1_11; const WRITE_MODE_MASK: u8 = 0b00000_1_00;
const READ_MODE_MASK: u8 = 0b_11111_0_11;
pub struct FourWire<ChipSelect: OutputPin> { pub struct FourWire<ChipSelect: OutputPin> {
cs: ChipSelect, cs: ChipSelect,
@ -44,9 +43,7 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
) -> Result<&'a mut [u8], nb::Error<Self::Error>> { ) -> Result<&'a mut [u8], nb::Error<Self::Error>> {
let mut control_phase = block << 3; let mut control_phase = block << 3;
if is_write { if is_write {
control_phase &= WRITE_MODE_MASK; control_phase |= WRITE_MODE_MASK;
} else {
control_phase &= READ_MODE_MASK;
} }
let data_phase = data; let data_phase = data;
let mut address_phase = [0u8; 2]; let mut address_phase = [0u8; 2];

19
src/bus/three_wire.rs
View file

@ -3,12 +3,11 @@ use embedded_hal::spi::FullDuplex;
use crate::bus::{ActiveBus, Bus}; use crate::bus::{ActiveBus, Bus};
const WRITE_MODE_MASK: u8 = 0b11111_1_11; const WRITE_MODE_MASK: u8 = 0b00000_1_0;
const READ_MODE_MASK: u8 = 0b_11111_0_11;
const FIXED_DATA_LENGTH_MODE_1: u8 = 0b111111_01; const FIXED_DATA_LENGTH_MODE_1: u8 = 0b000000_01;
const FIXED_DATA_LENGTH_MODE_2: u8 = 0b111111_10; const FIXED_DATA_LENGTH_MODE_2: u8 = 0b000000_10;
const FIXED_DATA_LENGTH_MODE_4: u8 = 0b111111_11; const FIXED_DATA_LENGTH_MODE_4: u8 = 0b000000_11;
pub struct ThreeWire {} pub struct ThreeWire {}
@ -53,22 +52,20 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
) -> Result<&'a mut [u8], nb::Error<Self::Error>> { ) -> Result<&'a mut [u8], nb::Error<Self::Error>> {
let mut control_phase = block << 3; let mut control_phase = block << 3;
if is_write { if is_write {
control_phase &= WRITE_MODE_MASK; control_phase |= WRITE_MODE_MASK;
} else {
control_phase &= READ_MODE_MASK;
} }
let mut data_phase = &mut data[..]; let mut data_phase = &mut data[..];
let mut last_length_written: u16; let mut last_length_written: u16;
while data_phase.len() > 0 { while data_phase.len() > 0 {
if data_phase.len() >= 4 { if data_phase.len() >= 4 {
control_phase &= FIXED_DATA_LENGTH_MODE_4; control_phase |= FIXED_DATA_LENGTH_MODE_4;
last_length_written = 4; last_length_written = 4;
} else if data_phase.len() >= 2 { } else if data_phase.len() >= 2 {
control_phase &= FIXED_DATA_LENGTH_MODE_2; control_phase |= FIXED_DATA_LENGTH_MODE_2;
last_length_written = 2; last_length_written = 2;
} else { } else {
control_phase &= FIXED_DATA_LENGTH_MODE_1; control_phase |= FIXED_DATA_LENGTH_MODE_1;
last_length_written = 1; last_length_written = 1;
} }