diff --git a/src/raw_device.rs b/src/raw_device.rs
index 25b09a9..c9e1224 100644
--- a/src/raw_device.rs
+++ b/src/raw_device.rs
@@ -39,6 +39,48 @@ impl<SpiBus: Bus> RawDevice<SpiBus> {
         Ok(Self { bus, raw_socket })
     }
 
+    /// Enable one or more interrupts
+    ///
+    /// # Args
+    /// * `which` - The interrupts to enable; see `register::socketn::Interrupt`
+    ///             For instance, pass `Interrupt::Receive` to get interrupts
+    ///             on packet reception only.
+    ///
+    pub fn enable_interrupt(&mut self, which: u8) -> Result<(), SpiBus::Error> {
+        self.raw_socket.set_interrupt_mask(&mut self.bus, which)?;
+        self.bus.write_frame(
+            register::COMMON,
+            register::common::SOCKET_INTERRUPT_MASK,
+            &[1],
+        )?;
+        Ok(())
+    }
+
+    /// Clear pending interrupts
+    ///
+    /// If using RTIC or similar, this should be called from the
+    /// interrupt handler. If not (i.e., if there's concern that this
+    /// use of the SPI bus will clobber someone else's use), then you
+    /// can mask the interrupt *at microcontroller level* in the
+    /// interrupt handler, then call this from thread mode before
+    /// unmasking again.
+    pub fn clear_interrupt(&mut self) -> Result<(), SpiBus::Error> {
+        self.raw_socket
+            .reset_interrupt(&mut self.bus, register::socketn::Interrupt::All)
+    }
+
+    /// Disable all interrupts
+    ///
+    pub fn disable_interrupt(&mut self) -> Result<(), SpiBus::Error> {
+        self.bus.write_frame(
+            register::COMMON,
+            register::common::SOCKET_INTERRUPT_MASK,
+            &[0],
+        )?;
+        self.raw_socket.set_interrupt_mask(&mut self.bus, 0xFF)?;
+        Ok(())
+    }
+
     /// Read an ethernet frame from the device.
     ///
     /// # Args
diff --git a/src/register.rs b/src/register.rs
index 3a1acfa..03b885b 100644
--- a/src/register.rs
+++ b/src/register.rs
@@ -22,6 +22,9 @@ pub mod common {
     /// Register: INTLEVEL (Interrupt Low Level Timer Register) [R/W] [0x0013 – 0x0014] [0x0000]
     pub const INTERRUPT_TIMER: u16 = 0x13;
 
+    /// Register: SIMR (Socket Interrupt Mask Register) [R/W] [0x0018] [0x00]
+    pub const SOCKET_INTERRUPT_MASK: u16 = 0x18;
+
     /// Register: RTR (Retry Time-value Register) [R/W] [0x0019 – 0x001A] [0x07D0]
     pub const RETRY_TIME: u16 = 0x19;