Added module containing new register address representations, added chip mode init/reset

src/bus/four_wire.rs

@@ -37,8 +37,8 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveBus for ActiveFourWire<Sp
     type Error = FourWireError<Spi::Error, ChipSelect::Error>;
     fn transfer_frame<'a>(
         &mut self,
-        address: u16,
         block: u8,
+        address: u16,
         is_write: bool,
         data: &'a mut [u8],
     ) -> Result<&'a mut [u8], nb::Error<Self::Error>> {

src/bus/mod.rs

@@ -16,8 +16,8 @@ pub trait ActiveBus {
 
     fn transfer_frame<'a>(
         &mut self,
-        address: u16,
         block: u8,
+        address: u16,
         is_write: bool,
         data: &'a mut [u8],
     ) -> Result<&'a mut [u8], Self::Error>;

src/bus/three_wire.rs

@@ -46,8 +46,8 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
     /// (address 29) AA
     fn transfer_frame<'a>(
         &mut self,
-        mut address: u16,
         block: u8,
+        mut address: u16,
         is_write: bool,
         data: &'a mut [u8],
     ) -> Result<&'a mut [u8], nb::Error<Self::Error>> {