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This commit is contained in:
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62e56052cf
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21 changed files with 1942 additions and 2121 deletions
13
.github/dependabot.yml
vendored
13
.github/dependabot.yml
vendored
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@ -1,13 +0,0 @@
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# To get started with Dependabot version updates, you'll need to specify which
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# package ecosystems to update and where the package manifests are located.
|
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# Please see the documentation for all configuration options:
|
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# https://help.github.com/github/administering-a-repository/configuration-options-for-dependency-updates
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version: 2
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updates:
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- package-ecosystem: cargo
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directory: "/"
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schedule:
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interval: daily
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time: "07:00"
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open-pull-requests-limit: 10
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70
.github/workflows/rust.yml
vendored
70
.github/workflows/rust.yml
vendored
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@ -1,70 +0,0 @@
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name: Rust
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on:
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push:
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branches: [ master ]
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pull_request:
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branches: [ master ]
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jobs:
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check:
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name: Check
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v3
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- uses: actions-rs/toolchain@v1
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with:
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profile: minimal
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toolchain: stable
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override: true
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- uses: actions-rs/cargo@v1
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with:
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command: check
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args: --all-features
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test:
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name: Test Suite
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v3
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- uses: actions-rs/toolchain@v1
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with:
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profile: minimal
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toolchain: stable
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override: true
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- uses: actions-rs/cargo@v1
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with:
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command: test
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args: --all-features
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fmt:
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name: Rustfmt
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v3
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- uses: actions-rs/toolchain@v1
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with:
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profile: minimal
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toolchain: stable
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override: true
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- run: rustup component add rustfmt
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- uses: actions-rs/cargo@v1
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with:
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command: fmt
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args: --all -- --check
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clippy:
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name: Clippy
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v3
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- uses: actions-rs/toolchain@v1
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with:
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profile: minimal
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toolchain: stable
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override: true
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- run: rustup component add clippy
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- uses: actions-rs/cargo@v1
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with:
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command: clippy
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args: -- -D warnings
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2
.gitignore
vendored
2
.gitignore
vendored
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@ -1,4 +1,2 @@
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*.iml
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/target
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/target
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**/*.rs.bk
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Cargo.lock
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Cargo.lock
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@ -13,7 +13,7 @@ keywords = ["embedded", "w5100", "embedded-hal-driver"]
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categories = ["embedded", "hardware-support", "no-std", "network-programming"]
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categories = ["embedded", "hardware-support", "no-std", "network-programming"]
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license = "AGPL-3.0-only"
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license = "AGPL-3.0-only"
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readme = "README.md"
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readme = "README.md"
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edition = "2018"
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edition = "2021"
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[features]
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[features]
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79
README.md
79
README.md
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@ -1,87 +1,12 @@
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# W5100 Driver
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# W5100 Driver
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Rust driver for the WIZnet W5100 Ethernet controler using SPI.
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**Fork status**:
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**Fork status**:
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* Work-in-progress fork of the crate [w5500](https://github.com/kellerkindt/w5500) for W5100. The two chips are different versions of the same design, very similar but not fully compatible. The older revision of the Arduino Ethernet Shield uses W5100, hence the need for this fork.
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* Work-in-progress fork of the crate [w5500](https://github.com/kellerkindt/w5500) for W5100. The two chips are different versions of the same design, very similar but not fully compatible. The older revision of the Arduino Ethernet Shield uses W5100, hence the need for this fork.
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* What works: receive and send UDP packets.
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* What works: receive and send UDP packets.
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* Tested on Arduino Uno with Arduino Ethernet Shield.
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* Tested on Arduino Uno with Arduino Ethernet Shield.
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This crate is a driver for the WIZnet W5500 chip. The W5500 chip is a hardwired TCP/IP embedded Ethernet controller
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that enables embedded systems using SPI (Serial Peripheral Interface) to access the LAN. It is one of the
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more popular ethernet modules on Arduino platforms.
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[](https://github.com/kellerkindt/w5500/actions?query=workflow%3ARust)
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[](https://github.com/kellerkindt/w5500)
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[](https://crates.io/crates/w5500)
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[](https://docs.rs/w5500)
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[](https://github.com/kellerkindt/w5500/issues/new)
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## Embedded-HAL
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The [`embedded-hal`](https://docs.rs/embedded-hal/latest/embedded_hal/index.html) is a standard set
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of traits meant to permit communication between MCU implementations and hardware drivers like this
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one. Any microcontroller that implements the
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[`spi::SpiDevice`](https://docs.rs/embedded-hal/latest/embedded_hal/spi/trait.SpiDevice.html) or
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[`spi::SpiBus`](https://docs.rs/embedded-hal/latest/embedded_hal/spi/trait.SpiBus.html) can use this
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driver.
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# Example Usage
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Below is a basic example of sending UDP packets to a remote host. An important thing to confirm is the configuration
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of the SPI implementation. It must be set up to work as the W5500 chip requires. That configuration is as follows:
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* Data Order: Most significant bit first
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* Clock Polarity: Idle low
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* Clock Phase: Sample leading edge
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* Clock speed: 33MHz maximum
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```rust,no_run
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use core::net::{IpAddr, Ipv4Addr, SocketAddr};
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#
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# struct Mock;
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#
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# impl embedded_hal::spi::ErrorType for Mock {
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# type Error = core::convert::Infallible;
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# }
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#
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# impl embedded_hal::spi::SpiDevice for Mock {
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# fn transaction(&mut self, operations: &mut [embedded_hal::spi::Operation<'_, u8>]) -> Result<(), Self::Error> {
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# Ok(())
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# }
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# }
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use embedded_nal::UdpClientStack;
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let mut spi = Mock;
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let mut device = w5500::UninitializedDevice::new(w5500::bus::FourWire::new(spi))
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.initialize_manual(
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w5500::MacAddress::new(0, 1, 2, 3, 4, 5),
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Ipv4Addr::new(192, 168, 86, 79),
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w5500::Mode::default()
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).unwrap();
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// Allocate a UDP socket to send data with
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let mut socket = device.socket().unwrap();
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// Connect the socket to the IP address and port we want to send to.
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device.connect(&mut socket,
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SocketAddr::new(IpAddr::V4(Ipv4Addr::new(192, 168, 86, 38)), 8000),
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).unwrap();
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// Send the data
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nb::block!(device.send(&mut socket, &[104, 101, 108, 108, 111, 10]));
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// Optionally close the socket
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device.close(socket);
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```
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## Todo
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In no particular order, things to do to improve this driver.
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* Add support for TCP server implementations
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* Add support for DHCP
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||||||
## License
|
## License
|
||||||
|
|
||||||
[Support me via LiberaPay](https://liberapay.com/tuxmain/donate)
|
[Support me via LiberaPay](https://liberapay.com/tuxmain/donate)
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||||||
|
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9
rustfmt.toml
Normal file
9
rustfmt.toml
Normal file
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@ -0,0 +1,9 @@
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|
hard_tabs = true
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|
newline_style = "Unix"
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imports_granularity = "Crate"
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unstable_features = true
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format_code_in_doc_comments = true
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format_macro_bodies = true
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format_macro_matchers = true
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format_strings = true
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|
@ -33,7 +33,7 @@ impl<SPI: SpiDevice> Bus for FourWire<SPI> {
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for (i, byte) in data.iter_mut().enumerate() {
|
for (i, byte) in data.iter_mut().enumerate() {
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self.spi.transaction(&mut [
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self.spi.transaction(&mut [
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Operation::Write(&[OPMODE_READ]),
|
Operation::Write(&[OPMODE_READ]),
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Operation::Write(&(address+i as u16).to_be_bytes()),
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Operation::Write(&(address + i as u16).to_be_bytes()),
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Operation::TransferInPlace(core::array::from_mut(byte)),
|
Operation::TransferInPlace(core::array::from_mut(byte)),
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])?;
|
])?;
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}
|
}
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|
@ -45,7 +45,7 @@ impl<SPI: SpiDevice> Bus for FourWire<SPI> {
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for (i, byte) in data.iter().enumerate() {
|
for (i, byte) in data.iter().enumerate() {
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self.spi.transaction(&mut [
|
self.spi.transaction(&mut [
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Operation::Write(&[OPMODE_WRITE]),
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Operation::Write(&[OPMODE_WRITE]),
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Operation::Write(&(address+i as u16).to_be_bytes()),
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Operation::Write(&(address + i as u16).to_be_bytes()),
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Operation::Write(&[*byte]),
|
Operation::Write(&[*byte]),
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])?;
|
])?;
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}
|
}
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|
|
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|
|
@ -1,6 +1,4 @@
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use crate::bus::Bus;
|
use crate::{bus::Bus, register::socketn::Command, socket::Socket};
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use crate::register::socketn::Command;
|
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use crate::socket::Socket;
|
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|
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pub(crate) struct RxCursor<'a, SpiBus>
|
pub(crate) struct RxCursor<'a, SpiBus>
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where
|
where
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|
|
@ -39,8 +37,7 @@ where
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}
|
}
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|
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let count = self.available().min(buf.len() as u16);
|
let count = self.available().min(buf.len() as u16);
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self.bus
|
self.bus.read_frame(self.ptr, &mut buf[..count as _])?;
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.read_frame(self.ptr, &mut buf[..count as _])?;
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Ok(self.skip(count))
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Ok(self.skip(count))
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}
|
}
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|
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|
@ -109,8 +106,7 @@ where
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}
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}
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let count = buf.len() as u16;
|
let count = buf.len() as u16;
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self.bus
|
self.bus.write_frame(self.ptr, &buf[..count as _])?;
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.write_frame(self.ptr, &buf[..count as _])?;
|
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self.ptr = self.ptr.wrapping_add(count);
|
self.ptr = self.ptr.wrapping_add(count);
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self.size -= count;
|
self.size -= count;
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Ok(count)
|
Ok(count)
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@ -1,12 +1,12 @@
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use bit_field::BitField;
|
use bit_field::BitField;
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|
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use crate::bus::{Bus, FourWire};
|
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use crate::host::Host;
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use crate::net::Ipv4Addr;
|
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use crate::socket::Socket;
|
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use crate::uninitialized_device::UninitializedDevice;
|
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use crate::{
|
use crate::{
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|
bus::{Bus, FourWire},
|
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|
host::Host,
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|
net::Ipv4Addr,
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register::{self, common::RetryTime},
|
register::{self, common::RetryTime},
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|
socket::Socket,
|
||||||
|
uninitialized_device::UninitializedDevice,
|
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MacAddress, Mode,
|
MacAddress, Mode,
|
||||||
};
|
};
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||||||
|
|
||||||
|
|
@ -132,8 +132,10 @@ impl<SpiBus: Bus, StateImpl: State> Device<SpiBus, StateImpl> {
|
||||||
|
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||||||
pub fn subnet_mask(&mut self) -> Result<Ipv4Addr, SpiBus::Error> {
|
pub fn subnet_mask(&mut self) -> Result<Ipv4Addr, SpiBus::Error> {
|
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let mut octets = [0u8; 4];
|
let mut octets = [0u8; 4];
|
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self.bus
|
self.bus.read_frame(
|
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.read_frame(register::COMMON + register::common::SUBNET_MASK, &mut octets)?;
|
register::COMMON + register::common::SUBNET_MASK,
|
||||||
|
&mut octets,
|
||||||
|
)?;
|
||||||
Ok(Ipv4Addr::from(octets))
|
Ok(Ipv4Addr::from(octets))
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -162,36 +164,28 @@ impl<SpiBus: Bus, StateImpl: State> Device<SpiBus, StateImpl> {
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn set_mode(&mut self, mode_options: Mode) -> Result<(), SpiBus::Error> {
|
pub fn set_mode(&mut self, mode_options: Mode) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus.write_frame(
|
||||||
register::COMMON +
|
register::COMMON + register::common::MODE,
|
||||||
register::common::MODE,
|
|
||||||
&mode_options.to_register(),
|
&mode_options.to_register(),
|
||||||
)
|
)
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn set_rx_memory_size(&mut self, val: u8) -> Result<(), SpiBus::Error> {
|
pub fn set_rx_memory_size(&mut self, val: u8) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus
|
||||||
register::COMMON +
|
.write_frame(register::COMMON + register::common::RX_MEMORY_SIZE, &[val])
|
||||||
register::common::RX_MEMORY_SIZE,
|
|
||||||
&[val],
|
|
||||||
)
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn set_tx_memory_size(&mut self, val: u8) -> Result<(), SpiBus::Error> {
|
pub fn set_tx_memory_size(&mut self, val: u8) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus
|
||||||
register::COMMON +
|
.write_frame(register::COMMON + register::common::TX_MEMORY_SIZE, &[val])
|
||||||
register::common::TX_MEMORY_SIZE,
|
|
||||||
&[val],
|
|
||||||
)
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn get_rx_memory_size(&mut self) -> Result<u8, SpiBus::Error> {
|
pub fn get_rx_memory_size(&mut self) -> Result<u8, SpiBus::Error> {
|
||||||
let mut val = [0];
|
let mut val = [0];
|
||||||
self.bus.read_frame(
|
self.bus.read_frame(
|
||||||
register::COMMON +
|
register::COMMON + register::common::RX_MEMORY_SIZE,
|
||||||
register::common::RX_MEMORY_SIZE,
|
|
||||||
&mut val,
|
&mut val,
|
||||||
)?;
|
)?;
|
||||||
Ok(val[0])
|
Ok(val[0])
|
||||||
|
|
@ -201,8 +195,7 @@ impl<SpiBus: Bus, StateImpl: State> Device<SpiBus, StateImpl> {
|
||||||
pub fn get_tx_memory_size(&mut self) -> Result<u8, SpiBus::Error> {
|
pub fn get_tx_memory_size(&mut self) -> Result<u8, SpiBus::Error> {
|
||||||
let mut val = [0];
|
let mut val = [0];
|
||||||
self.bus.read_frame(
|
self.bus.read_frame(
|
||||||
register::COMMON +
|
register::COMMON + register::common::TX_MEMORY_SIZE,
|
||||||
register::common::TX_MEMORY_SIZE,
|
|
||||||
&mut val,
|
&mut val,
|
||||||
)?;
|
)?;
|
||||||
Ok(val[0])
|
Ok(val[0])
|
||||||
|
|
@ -227,8 +220,7 @@ impl<SpiBus: Bus, StateImpl: State> Device<SpiBus, StateImpl> {
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn set_retry_timeout(&mut self, retry_time_value: RetryTime) -> Result<(), SpiBus::Error> {
|
pub fn set_retry_timeout(&mut self, retry_time_value: RetryTime) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus.write_frame(
|
||||||
register::COMMON +
|
register::COMMON + register::common::RETRY_TIME,
|
||||||
register::common::RETRY_TIME,
|
|
||||||
&retry_time_value.to_register(),
|
&retry_time_value.to_register(),
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
@ -244,8 +236,7 @@ impl<SpiBus: Bus, StateImpl: State> Device<SpiBus, StateImpl> {
|
||||||
pub fn current_retry_timeout(&mut self) -> Result<RetryTime, SpiBus::Error> {
|
pub fn current_retry_timeout(&mut self) -> Result<RetryTime, SpiBus::Error> {
|
||||||
let mut retry_time_register: [u8; 2] = [0, 0];
|
let mut retry_time_register: [u8; 2] = [0, 0];
|
||||||
self.bus.read_frame(
|
self.bus.read_frame(
|
||||||
register::COMMON+
|
register::COMMON + register::common::RETRY_TIME,
|
||||||
register::common::RETRY_TIME,
|
|
||||||
&mut retry_time_register,
|
&mut retry_time_register,
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
@ -270,8 +261,7 @@ impl<SpiBus: Bus, StateImpl: State> Device<SpiBus, StateImpl> {
|
||||||
/// `RCR = 0x0007`
|
/// `RCR = 0x0007`
|
||||||
pub fn set_retry_count(&mut self, retry_count: u8) -> Result<(), SpiBus::Error> {
|
pub fn set_retry_count(&mut self, retry_count: u8) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus.write_frame(
|
||||||
register::COMMON+
|
register::COMMON + register::common::RETRY_COUNT,
|
||||||
register::common::RETRY_COUNT,
|
|
||||||
&[retry_count],
|
&[retry_count],
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
@ -288,8 +278,7 @@ impl<SpiBus: Bus, StateImpl: State> Device<SpiBus, StateImpl> {
|
||||||
pub fn current_retry_count(&mut self) -> Result<u8, SpiBus::Error> {
|
pub fn current_retry_count(&mut self) -> Result<u8, SpiBus::Error> {
|
||||||
let mut retry_count_register: [u8; 1] = [0];
|
let mut retry_count_register: [u8; 1] = [0];
|
||||||
self.bus.read_frame(
|
self.bus.read_frame(
|
||||||
register::COMMON+
|
register::COMMON + register::common::RETRY_COUNT,
|
||||||
register::common::RETRY_COUNT,
|
|
||||||
&mut retry_count_register,
|
&mut retry_count_register,
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,4 @@
|
||||||
use crate::bus::Bus;
|
use crate::{bus::Bus, host::Host, MacAddress};
|
||||||
use crate::host::Host;
|
|
||||||
use crate::MacAddress;
|
|
||||||
|
|
||||||
#[derive(Debug)]
|
#[derive(Debug)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,10 @@
|
||||||
use core::net::Ipv4Addr;
|
use core::net::Ipv4Addr;
|
||||||
|
|
||||||
use crate::bus::Bus;
|
use crate::{
|
||||||
use crate::host::{Host, HostConfig};
|
bus::Bus,
|
||||||
use crate::MacAddress;
|
host::{Host, HostConfig},
|
||||||
|
MacAddress,
|
||||||
|
};
|
||||||
|
|
||||||
#[derive(Debug)]
|
#[derive(Debug)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
|
|
|
||||||
|
|
@ -3,11 +3,8 @@ use core::net::Ipv4Addr;
|
||||||
mod dhcp;
|
mod dhcp;
|
||||||
mod manual;
|
mod manual;
|
||||||
|
|
||||||
pub use self::dhcp::Dhcp;
|
pub use self::{dhcp::Dhcp, manual::Manual};
|
||||||
pub use self::manual::Manual;
|
use crate::{bus::Bus, register, MacAddress};
|
||||||
use crate::bus::Bus;
|
|
||||||
use crate::register;
|
|
||||||
use crate::MacAddress;
|
|
||||||
|
|
||||||
#[derive(Debug)]
|
#[derive(Debug)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
|
|
|
||||||
|
|
@ -32,11 +32,8 @@ impl<SpiBus: Bus> RawDevice<SpiBus> {
|
||||||
|
|
||||||
/// Enable one or more interrupts
|
/// Enable one or more interrupts
|
||||||
pub fn enable_interrupts(&mut self) -> Result<(), SpiBus::Error> {
|
pub fn enable_interrupts(&mut self) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus
|
||||||
register::COMMON +
|
.write_frame(register::COMMON + register::common::INTERRUPT_MASK, &[1])?;
|
||||||
register::common::INTERRUPT_MASK,
|
|
||||||
&[1],
|
|
||||||
)?;
|
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -54,13 +51,9 @@ impl<SpiBus: Bus> RawDevice<SpiBus> {
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Disable all interrupts
|
/// Disable all interrupts
|
||||||
///
|
|
||||||
pub fn disable_interrupts(&mut self) -> Result<(), SpiBus::Error> {
|
pub fn disable_interrupts(&mut self) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus
|
||||||
register::COMMON +
|
.write_frame(register::COMMON + register::common::INTERRUPT_MASK, &[0])?;
|
||||||
register::common::INTERRUPT_MASK,
|
|
||||||
&[0],
|
|
||||||
)?;
|
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -186,7 +186,6 @@ pub mod socketn {
|
||||||
/// > and passive-close.
|
/// > and passive-close.
|
||||||
/// > When Disconnect-process is successfully completed, or
|
/// > When Disconnect-process is successfully completed, or
|
||||||
/// > when timeout occurs, these change to SOCK_CLOSED.
|
/// > when timeout occurs, these change to SOCK_CLOSED.
|
||||||
///
|
|
||||||
#[derive(TryFromPrimitive, Debug, Copy, Clone, PartialEq, Eq)]
|
#[derive(TryFromPrimitive, Debug, Copy, Clone, PartialEq, Eq)]
|
||||||
#[repr(u8)]
|
#[repr(u8)]
|
||||||
pub enum Status {
|
pub enum Status {
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,9 @@
|
||||||
use core::convert::TryFrom;
|
use core::{convert::TryFrom, net::Ipv4Addr};
|
||||||
use core::net::Ipv4Addr;
|
|
||||||
|
|
||||||
use crate::bus::Bus;
|
use crate::{
|
||||||
use crate::register::{self, socketn};
|
bus::Bus,
|
||||||
|
register::{self, socketn},
|
||||||
|
};
|
||||||
|
|
||||||
#[derive(Debug)]
|
#[derive(Debug)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
|
|
@ -13,9 +14,7 @@ pub struct Socket {
|
||||||
impl Socket {
|
impl Socket {
|
||||||
/// 4 sockets available on the w5100
|
/// 4 sockets available on the w5100
|
||||||
pub fn new(index: u8) -> Self {
|
pub fn new(index: u8) -> Self {
|
||||||
Socket {
|
Socket { index }
|
||||||
index,
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn register(&self) -> u16 {
|
pub fn register(&self) -> u16 {
|
||||||
|
|
@ -32,12 +31,9 @@ impl Socket {
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn get_mode<SpiBus: Bus>(
|
pub fn get_mode<SpiBus: Bus>(&self, bus: &mut SpiBus) -> Result<u8, SpiBus::Error> {
|
||||||
&self,
|
|
||||||
bus: &mut SpiBus,
|
|
||||||
) -> Result<u8, SpiBus::Error> {
|
|
||||||
let mut mode = [0];
|
let mut mode = [0];
|
||||||
bus.write_frame(self.register() + socketn::MODE, &mut mode)?;
|
bus.write_frame(self.register() + socketn::MODE, &mode)?;
|
||||||
Ok(mode[0])
|
Ok(mode[0])
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -78,10 +74,7 @@ impl Socket {
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn get_source_port<SpiBus: Bus>(
|
pub fn get_source_port<SpiBus: Bus>(&self, bus: &mut SpiBus) -> Result<u16, SpiBus::Error> {
|
||||||
&self,
|
|
||||||
bus: &mut SpiBus,
|
|
||||||
) -> Result<u16, SpiBus::Error> {
|
|
||||||
let mut data = [0; 2];
|
let mut data = [0; 2];
|
||||||
bus.read_frame(self.register() + socketn::SOURCE_PORT, &mut data)?;
|
bus.read_frame(self.register() + socketn::SOURCE_PORT, &mut data)?;
|
||||||
Ok(u16::from_be_bytes(data))
|
Ok(u16::from_be_bytes(data))
|
||||||
|
|
@ -158,23 +151,23 @@ impl Socket {
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn enable_interrupts<SpiBus: Bus>(
|
pub fn enable_interrupts<SpiBus: Bus>(&self, bus: &mut SpiBus) -> Result<(), SpiBus::Error> {
|
||||||
&self,
|
|
||||||
bus: &mut SpiBus,
|
|
||||||
) -> Result<(), SpiBus::Error> {
|
|
||||||
let mut data = [0];
|
let mut data = [0];
|
||||||
bus.read_frame(register::COMMON + register::common::INTERRUPT_MASK, &mut data)?;
|
bus.read_frame(
|
||||||
|
register::COMMON + register::common::INTERRUPT_MASK,
|
||||||
|
&mut data,
|
||||||
|
)?;
|
||||||
data[0] |= 1 << self.index;
|
data[0] |= 1 << self.index;
|
||||||
bus.write_frame(register::COMMON + register::common::INTERRUPT_MASK, &data)?;
|
bus.write_frame(register::COMMON + register::common::INTERRUPT_MASK, &data)?;
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn disable_interrupts<SpiBus: Bus>(
|
pub fn disable_interrupts<SpiBus: Bus>(&self, bus: &mut SpiBus) -> Result<(), SpiBus::Error> {
|
||||||
&self,
|
|
||||||
bus: &mut SpiBus,
|
|
||||||
) -> Result<(), SpiBus::Error> {
|
|
||||||
let mut data = [0];
|
let mut data = [0];
|
||||||
bus.read_frame(register::COMMON + register::common::INTERRUPT_MASK, &mut data)?;
|
bus.read_frame(
|
||||||
|
register::COMMON + register::common::INTERRUPT_MASK,
|
||||||
|
&mut data,
|
||||||
|
)?;
|
||||||
data[0] &= !(1 << self.index);
|
data[0] &= !(1 << self.index);
|
||||||
bus.write_frame(register::COMMON + register::common::INTERRUPT_MASK, &data)?;
|
bus.write_frame(register::COMMON + register::common::INTERRUPT_MASK, &data)?;
|
||||||
Ok(())
|
Ok(())
|
||||||
|
|
|
||||||
31
src/udp.rs
31
src/udp.rs
|
|
@ -88,12 +88,10 @@ impl UdpSocket {
|
||||||
self.socket.reset_interrupt(bus, socketn::Interrupt::All)?;
|
self.socket.reset_interrupt(bus, socketn::Interrupt::All)?;
|
||||||
self.socket.set_source_port(bus, self.port)?;
|
self.socket.set_source_port(bus, self.port)?;
|
||||||
self.socket.set_mode(bus, socketn::Protocol::Udp)?;
|
self.socket.set_mode(bus, socketn::Protocol::Udp)?;
|
||||||
self.socket.enable_interrupts(
|
self.socket.enable_interrupts(bus)?;
|
||||||
bus
|
|
||||||
)?;
|
|
||||||
self.socket.command(bus, socketn::Command::Open)?;
|
self.socket.command(bus, socketn::Command::Open)?;
|
||||||
if self.socket.get_status(bus)? == Status::Udp as u8 {
|
if self.socket.get_status(bus)? == Status::Udp as u8 {
|
||||||
return Ok(())
|
return Ok(());
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -127,7 +125,6 @@ impl UdpSocket {
|
||||||
// We set this variable to true when:
|
// We set this variable to true when:
|
||||||
/// - We have the same Socket address already set
|
/// - We have the same Socket address already set
|
||||||
/// - We don't have any previous destination set
|
/// - We don't have any previous destination set
|
||||||
///
|
|
||||||
// either no previous destination is set or a new one
|
// either no previous destination is set or a new one
|
||||||
if self
|
if self
|
||||||
.destination
|
.destination
|
||||||
|
|
@ -245,12 +242,16 @@ impl UdpSocket {
|
||||||
if offset as usize + write_data.len() > 0x800 {
|
if offset as usize + write_data.len() > 0x800 {
|
||||||
let upper_size = 0x800 - offset as usize;
|
let upper_size = 0x800 - offset as usize;
|
||||||
bus.write_frame(start_addr, &write_data[0..upper_size])?;
|
bus.write_frame(start_addr, &write_data[0..upper_size])?;
|
||||||
bus.write_frame(0x4000 + 0x800 * self.socket.index as u16, &write_data[upper_size..])?;
|
bus.write_frame(
|
||||||
|
0x4000 + 0x800 * self.socket.index as u16,
|
||||||
|
&write_data[upper_size..],
|
||||||
|
)?;
|
||||||
} else {
|
} else {
|
||||||
bus.write_frame(start_addr, write_data)?;
|
bus.write_frame(start_addr, write_data)?;
|
||||||
}
|
}
|
||||||
|
|
||||||
self.socket.set_tx_write_pointer(bus, offset.wrapping_add(write_data.len() as u16))?;
|
self.socket
|
||||||
|
.set_tx_write_pointer(bus, offset.wrapping_add(write_data.len() as u16))?;
|
||||||
|
|
||||||
self.block_send_command(bus)?;
|
self.block_send_command(bus)?;
|
||||||
self.socket.reset_interrupt(bus, socketn::Interrupt::SendOk);
|
self.socket.reset_interrupt(bus, socketn::Interrupt::SendOk);
|
||||||
|
|
@ -566,13 +567,23 @@ where
|
||||||
SpiBus: Bus,
|
SpiBus: Bus,
|
||||||
StateImpl: State,
|
StateImpl: State,
|
||||||
{
|
{
|
||||||
pub fn get_port(&mut self, socket: &mut UdpSocket) -> Result<u16, UdpSocketError<SpiBus::Error>> {
|
pub fn get_port(
|
||||||
|
&mut self,
|
||||||
|
socket: &mut UdpSocket,
|
||||||
|
) -> Result<u16, UdpSocketError<SpiBus::Error>> {
|
||||||
Ok(socket.get_port_for_real(&mut self.bus)?)
|
Ok(socket.get_port_for_real(&mut self.bus)?)
|
||||||
}
|
}
|
||||||
pub fn get_receive_size(&mut self, socket: &mut UdpSocket) -> Result<u16, UdpSocketError<SpiBus::Error>> {
|
pub fn get_receive_size(
|
||||||
|
&mut self,
|
||||||
|
socket: &mut UdpSocket,
|
||||||
|
) -> Result<u16, UdpSocketError<SpiBus::Error>> {
|
||||||
Ok(socket.socket.get_receive_size(&mut self.bus)?)
|
Ok(socket.socket.get_receive_size(&mut self.bus)?)
|
||||||
}
|
}
|
||||||
pub fn has_interrupt(&mut self, socket: &mut UdpSocket, interrupt: socketn::Interrupt) -> Result<bool, UdpSocketError<SpiBus::Error>> {
|
pub fn has_interrupt(
|
||||||
|
&mut self,
|
||||||
|
socket: &mut UdpSocket,
|
||||||
|
interrupt: socketn::Interrupt,
|
||||||
|
) -> Result<bool, UdpSocketError<SpiBus::Error>> {
|
||||||
Ok(socket.socket.has_interrupt(&mut self.bus, interrupt)?)
|
Ok(socket.socket.has_interrupt(&mut self.bus, interrupt)?)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -2,11 +2,11 @@ use core::net::Ipv4Addr;
|
||||||
|
|
||||||
use embedded_hal::spi::SpiDevice;
|
use embedded_hal::spi::SpiDevice;
|
||||||
|
|
||||||
use crate::bus::{Bus, FourWire};
|
|
||||||
use crate::device::{Device, DeviceState};
|
|
||||||
use crate::host::{Dhcp, Host, Manual};
|
|
||||||
use crate::raw_device::RawDevice;
|
|
||||||
use crate::{
|
use crate::{
|
||||||
|
bus::{Bus, FourWire},
|
||||||
|
device::{Device, DeviceState},
|
||||||
|
host::{Dhcp, Host, Manual},
|
||||||
|
raw_device::RawDevice,
|
||||||
register::{self, common::RetryTime},
|
register::{self, common::RetryTime},
|
||||||
MacAddress, Mode,
|
MacAddress, Mode,
|
||||||
};
|
};
|
||||||
|
|
@ -93,7 +93,6 @@ impl<SpiBus: Bus> UninitializedDevice<SpiBus> {
|
||||||
mut host: HostImpl,
|
mut host: HostImpl,
|
||||||
mode_options: Mode,
|
mode_options: Mode,
|
||||||
) -> Result<Device<SpiBus, DeviceState<HostImpl>>, InitializeError<SpiBus::Error>> {
|
) -> Result<Device<SpiBus, DeviceState<HostImpl>>, InitializeError<SpiBus::Error>> {
|
||||||
|
|
||||||
// RESET
|
// RESET
|
||||||
self.reset()?;
|
self.reset()?;
|
||||||
|
|
||||||
|
|
@ -127,8 +126,7 @@ impl<SpiBus: Bus> UninitializedDevice<SpiBus> {
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn set_mode(&mut self, mode_options: Mode) -> Result<(), SpiBus::Error> {
|
pub fn set_mode(&mut self, mode_options: Mode) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus.write_frame(
|
||||||
register::COMMON +
|
register::COMMON + register::common::MODE,
|
||||||
register::common::MODE,
|
|
||||||
&mode_options.to_register(),
|
&mode_options.to_register(),
|
||||||
)
|
)
|
||||||
}
|
}
|
||||||
|
|
@ -150,8 +148,7 @@ impl<SpiBus: Bus> UninitializedDevice<SpiBus> {
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn set_retry_timeout(&mut self, retry_time_value: RetryTime) -> Result<(), SpiBus::Error> {
|
pub fn set_retry_timeout(&mut self, retry_time_value: RetryTime) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus.write_frame(
|
||||||
register::COMMON +
|
register::COMMON + register::common::RETRY_TIME,
|
||||||
register::common::RETRY_TIME,
|
|
||||||
&retry_time_value.to_register(),
|
&retry_time_value.to_register(),
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
@ -165,8 +162,7 @@ impl<SpiBus: Bus> UninitializedDevice<SpiBus> {
|
||||||
pub fn current_retry_timeout(&mut self) -> Result<RetryTime, SpiBus::Error> {
|
pub fn current_retry_timeout(&mut self) -> Result<RetryTime, SpiBus::Error> {
|
||||||
let mut retry_time_register: [u8; 2] = [0, 0];
|
let mut retry_time_register: [u8; 2] = [0, 0];
|
||||||
self.bus.read_frame(
|
self.bus.read_frame(
|
||||||
register::COMMON+
|
register::COMMON + register::common::RETRY_TIME,
|
||||||
register::common::RETRY_TIME,
|
|
||||||
&mut retry_time_register,
|
&mut retry_time_register,
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
@ -191,8 +187,7 @@ impl<SpiBus: Bus> UninitializedDevice<SpiBus> {
|
||||||
/// `RCR = 0x0007`
|
/// `RCR = 0x0007`
|
||||||
pub fn set_retry_count(&mut self, retry_count: u8) -> Result<(), SpiBus::Error> {
|
pub fn set_retry_count(&mut self, retry_count: u8) -> Result<(), SpiBus::Error> {
|
||||||
self.bus.write_frame(
|
self.bus.write_frame(
|
||||||
register::COMMON+
|
register::COMMON + register::common::RETRY_COUNT,
|
||||||
register::common::RETRY_COUNT,
|
|
||||||
&[retry_count],
|
&[retry_count],
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
@ -208,8 +203,7 @@ impl<SpiBus: Bus> UninitializedDevice<SpiBus> {
|
||||||
pub fn current_retry_count(&mut self) -> Result<u8, SpiBus::Error> {
|
pub fn current_retry_count(&mut self) -> Result<u8, SpiBus::Error> {
|
||||||
let mut retry_count_register: [u8; 1] = [0];
|
let mut retry_count_register: [u8; 1] = [0];
|
||||||
self.bus.read_frame(
|
self.bus.read_frame(
|
||||||
register::COMMON+
|
register::COMMON + register::common::RETRY_COUNT,
|
||||||
register::common::RETRY_COUNT,
|
|
||||||
&mut retry_count_register,
|
&mut retry_count_register,
|
||||||
)?;
|
)?;
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue