tuxmain/w5100-rs
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Implemented From trait for busses

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This commit is contained in:
Jonah Dahlquist 2020-11-24 20:28:18 -08:00
commit 90604fc86a
2 changed files with 10 additions and 6 deletions
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2
src/bus/four_wire.rs
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@ -69,6 +69,7 @@ impl<Spi: FullDuplex<u8>, ChipSelect: OutputPin> ActiveFourWire<Spi, ChipSelect>
}
}
// Must use map_err, ambiguity prevents From from being implemented
#[repr(u8)]
pub enum FourWireError<SpiError, ChipSelectError> {
SpiError(SpiError),
@ -87,4 +88,3 @@ impl<SpiError, ChipSelectError> fmt::Debug for FourWireError<SpiError, ChipSelec
)
}
}
// TODO impl From and remove map_errs

14
src/bus/three_wire.rs
View file

@ -81,8 +81,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
&mut self.spi,
&mut data_phase[..last_length_written as usize],
)
})
.map_err(ThreeWireError::SpiError)?;
})?;
address += last_length_written;
data_phase = &mut data_phase[last_length_written as usize..];
@ -111,8 +110,7 @@ impl<Spi: FullDuplex<u8>> ActiveBus for ActiveThreeWire<Spi> {
.and_then(|_| Self::transfer_byte(&mut self.spi, control_phase))
.and_then(|_| {
Self::write_bytes(&mut self.spi, &data_phase[..last_length_written as usize])
})
.map_err(ThreeWireError::SpiError)?;
})?;
address += last_length_written;
data_phase = &data_phase[last_length_written as usize..];
@ -130,6 +128,13 @@ impl<Spi: FullDuplex<u8>> ActiveThreeWire<Spi> {
pub enum ThreeWireError<SpiError> {
SpiError(SpiError),
}
impl<SpiError> From<SpiError> for ThreeWireError<SpiError> {
fn from(error: SpiError) -> ThreeWireError<SpiError> {
ThreeWireError::SpiError(error)
}
}
impl<SpiError> fmt::Debug for ThreeWireError<SpiError> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
write!(
@ -141,4 +146,3 @@ impl<SpiError> fmt::Debug for ThreeWireError<SpiError> {
)
}
}
// TODO impl From and remove map_errs