diff --git a/src/bus/four_wire.rs b/src/bus/four_wire.rs index 43bba2c..601fe97 100644 --- a/src/bus/four_wire.rs +++ b/src/bus/four_wire.rs @@ -32,30 +32,34 @@ impl + Write, ChipSelect: OutputPin> Bus for FourWire Result<(), Self::Error> { let address_phase = address.to_be_bytes(); let control_phase = block << 3 | WRITE_MODE_MASK; let data_phase = data; self.cs.set_low().map_err(FourWireError::ChipSelectError)?; - self.spi - .write(&address_phase) - .and_then(|_| self.spi.write(&[control_phase])) - .and_then(|_| self.spi.write(data_phase)) - .map_err(FourWireError::WriteError)?; + let result = (|| { + self.spi + .write(&address_phase) + .and_then(|_| self.spi.write(&[control_phase])) + .and_then(|_| self.spi.write(data_phase)) + .map_err(FourWireError::WriteError)?; + Ok(()) + })(); self.cs.set_high().map_err(FourWireError::ChipSelectError)?; - - Ok(()) + result } }